The DAC5682Z is a dual-channel 16-bit 1.0 GSPS DAC with wideband LVDS data input,
integrated 2x/4x interpolation filters, onboard clock multiplier, and internal voltage reference.
The DAC5682Z offers superior linearity, noise, crosstalk, and PLL phase noise performance.
The DAC5682Z integrates a wideband LVDS port with on-chip termination. Full-rate input
data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be
interpolated by onboard 2x or 4x FIR filters. Each interpolation FIR is configurable in either
low-pass or high-pass mode, allowing selection of a higher order output spectral image. An on-chip
delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data
clock.
The DAC5682Z allows both complex or real output. An optional Fs/4 coarse mixer in complex
mode provides coarse frequency upconversion and the dual DAC output produces a complex Hilbert
Transform pair. An external RF quadrature modulator then performs the final single sideband
up-conversion. The interpolation filters and complex coarse mixers efficiently provide frequency
plan flexibility while enabling higher output DAC rates to simplify image rejection
filtering.
The DAC5682Z is characterized for operation over the industrial temperature range of
40°C to 85°C and is available in a 64-pin QFN package. Other single-channel members of the family
include the interpolating DAC5681Z and the noninterpolating DAC5681.
The DAC5682Z is a dual-channel 16-bit 1.0 GSPS DAC with wideband LVDS data input,
integrated 2x/4x interpolation filters, onboard clock multiplier, and internal voltage reference.
The DAC5682Z offers superior linearity, noise, crosstalk, and PLL phase noise performance.
The DAC5682Z integrates a wideband LVDS port with on-chip termination. Full-rate input
data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be
interpolated by onboard 2x or 4x FIR filters. Each interpolation FIR is configurable in either
low-pass or high-pass mode, allowing selection of a higher order output spectral image. An on-chip
delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data
clock.
The DAC5682Z allows both complex or real output. An optional Fs/4 coarse mixer in complex
mode provides coarse frequency upconversion and the dual DAC output produces a complex Hilbert
Transform pair. An external RF quadrature modulator then performs the final single sideband
up-conversion. The interpolation filters and complex coarse mixers efficiently provide frequency
plan flexibility while enabling higher output DAC rates to simplify image rejection
filtering.
The DAC5682Z is characterized for operation over the industrial temperature range of
40°C to 85°C and is available in a 64-pin QFN package. Other single-channel members of the family
include the interpolating DAC5681Z and the noninterpolating DAC5681.