ADC12xJ1600-Q1 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600-Q1 suited for light detection and ranging (LiDAR) systems. ADC12xJ1600-Q1 is qualified for automotive applications.
Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | ADC12xJ1600-Q1 Quad, Dual, Single Channel, 1.6GSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. B) | PDF | HTML | 22 Oct 2024 |
| Application brief | Time of Flight and LIDAR - Optical Front End Design (Rev. A) | PDF | HTML | 29 Apr 2022 | |
| Application note | Powering Noise Sensitive LIDAR ADC Designs With TPS62913 Buck Converter | PDF | HTML | 28 Feb 2022 | |
| Technical article | Keys to quick success using high-speed data converters | PDF | HTML | 13 Oct 2020 | |
| EVM User's guide | TSW12QJ1600 Evaluation Module User's Guide | 20 Jul 2020 |
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The ADC12QJ1600 evaluation module (EVM) allows for the evaluation of the ADC12QJ1600-Q1 product. ADC12QJ1600-Q1 is a low-power, 12-bit, quad-channel, 1.6-GSPS analog-to-digital converter (ADC) with a buffered analog input and integrated digital down converter with on-chip PLL, which features a (...)
The TSW12QJ1600 evaluation module (EVM) is used to evaluate the ADC12QJ1600-Q1 analog-to-digital converter (ADC) with different front-end options. ADC12QJ1600-Q1 is a 12-bit ADC capable of operating at sampling rates up to 1.6 gigasample per second (GSPS) with four analog input channels.
This design (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
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