The DAC34SH84 is a very low-power, high-dynamic range, quad-channel, 16-bit
digital-to-analog converter (DAC) with a sample rate as high as 1.5 GSPS.
The device includes features that simplify the design of complex transmit architectures:
2× to 16× digital interpolation filters with over 90 dB of stop-band attenuation simplify the data
interface and reconstruction filters. Independent complex mixers allow flexible carrier
placement.
A high-performance low-jitter clock multiplier simplifies clocking of the device without
significant impact on the dynamic range. The digital quadrature modulator correction (QMC) enables
complete IQ compensation for gain, offset and phase between channels in direct upconversion
applications.
Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip
termination. The wide bus allows the processing of high-bandwidth signals. The device includes a
FIFO, data pattern checker, and parity test to ease the input interface. The interface also allows
full synchronization of multiple devices.
The device is characterized for operation over the entire industrial temperature range of
–40°C to 85°C and is available in a 196-ball, 12-mm × 12-mm, 0.8-mm pitch NFBGA package.
The DAC34SH84 low-power, high-bandwidth support, superior crosstalk, high dynamic range,
and features are an ideal fit for next-generation communication systems.
The DAC34SH84 is a very low-power, high-dynamic range, quad-channel, 16-bit
digital-to-analog converter (DAC) with a sample rate as high as 1.5 GSPS.
The device includes features that simplify the design of complex transmit architectures:
2× to 16× digital interpolation filters with over 90 dB of stop-band attenuation simplify the data
interface and reconstruction filters. Independent complex mixers allow flexible carrier
placement.
A high-performance low-jitter clock multiplier simplifies clocking of the device without
significant impact on the dynamic range. The digital quadrature modulator correction (QMC) enables
complete IQ compensation for gain, offset and phase between channels in direct upconversion
applications.
Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip
termination. The wide bus allows the processing of high-bandwidth signals. The device includes a
FIFO, data pattern checker, and parity test to ease the input interface. The interface also allows
full synchronization of multiple devices.
The device is characterized for operation over the entire industrial temperature range of
–40°C to 85°C and is available in a 196-ball, 12-mm × 12-mm, 0.8-mm pitch NFBGA package.
The DAC34SH84 low-power, high-bandwidth support, superior crosstalk, high dynamic range,
and features are an ideal fit for next-generation communication systems.