CODELOADER
CodeLoader Software for device register programming
CODELOADER
Overview
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | Loop filter & device configuration + simulation | Device register programming |
LMX24xx PLL family | EasyPLL | CodeLoader* |
LMX25xx PLL+VCO family | ||
LMK jitter cleaners and distributors |
*For new designs, use the Clocks and Synthesizers (TICS) Pro Software tool.
Downloads
Additional resources you might need
PLLATINUMSIM-SW — PLLatinum Sim Tool
Supported products & hardware
Products
Clock buffers
Clock generators
Clock jitter cleaners
Clock network synchronizers
IQ demodulators
RF PLLs & synthesizers
Hardware development
Evaluation board
PLLATINUMSIM-SW — PLLatinum Sim Tool
Products
Clock buffers
Clock generators
Clock jitter cleaners
Clock network synchronizers
IQ demodulators
RF PLLs & synthesizers
Hardware development
Evaluation board
Documentation
Release Information
Bug fixes
What's new
- Fixed Kvco calculation bug introduced in 1.6.6
- Added warning for loop bandwidth being restricted due to min high order capacitance.
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
Supported products & hardware
Products
Clock buffers
Clock generators
Clock jitter cleaners
Clock network synchronizers
Oscillators
RF PLLs & synthesizers
Hardware development
Evaluation board
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.8.0 installer binary for Windows operating system
Products
Clock buffers
Clock generators
Clock jitter cleaners
Clock network synchronizers
Oscillators
RF PLLs & synthesizers
Hardware development
Evaluation board
Documentation
TICS Pro 1.7.8.0 Software Manifest
TICS Pro 1.7.8.0 Release Notes
Release Information
Added
- LMK5C23208A
Improvements
- TCP server returns error descriptions
- TICSPro_TCP.py updated for python ≥ 3.10. Remove type annotations if backward compatibility with older python versions is required.
- LMK5B/5C:
- Warn when GPIOx selects REFx monitor, but REFx is not programmed
- Relative calculation of DPLLx_PH_OFFSET value
- Added fields and improved frequency planning for 1-PPS outputs
- PLLx_RDIV_MUX_SEL only sets recommended values when dropdown is changed; no longer changed by DPLL loop filter calculation or TCS file load
- Advanced Options checkbox added on Getting Started page
- GPIOx descriptions updated for accuracy
- LMK5B12212, LMK5C12212A:
- New step added to Start Page process to reduce current consumption and noise
- SRAM sequence EEPROM generation sets optimized values from new step in Start Page process
- LMK5B33414, LMK5C33414A:
- Simplified programming sequence by combining writes for the output divider synchronization sequence generator
Bug Fixes
- LMK5B12212, LMK5C12212A:
- Some controls which were not register-backed have been updated to be register-backed.
- LMK5B33414, LMK5C33414A:
- Fixed "Set SYNC Enable" buttons on "SYNC/SYSREF/1-PPS" page
Known Issues
- LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
Technical article | A survival guide to scaling your PLL loop filter design | PDF | HTML | Nov 22, 2016 | |
Technical article | What to do when your PLL does not lock | PDF | HTML | Jul 12, 2016 | |
User guide | CodeLoader 4 Operating Instructions User's Guide (Rev. A) | Jul 21, 2014 |
Related design resources
Hardware development
EVALUATION BOARD
Support & training
TI E2E™ forums with technical support from TI engineers
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