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CDCLVD1212

ACTIVE

Low jitter, 2-input selectable 1:12 universal-to-LVDS buffer

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Data sheet

CDCLVD1212

ACTIVE
Data sheet Order now

Product details

Function Differential Additive RMS jitter (typ) (fs) 171 Output frequency (max) (MHz) 800 Number of outputs 12 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 35 Features 2:12 fanout, Universal inputs Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
Function Differential Additive RMS jitter (typ) (fs) 171 Output frequency (max) (MHz) 800 Number of outputs 12 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 35 Features 2:12 fanout, Universal inputs Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
VQFN (RHA) 40 36 mm² 6 x 6
  • 2:12 Differential Buffer
  • Low Additive Jitter: < 300-fs RMS in
    10-kHz to 20-MHz
  • Low Output Skew of 35 ps (Maximum)
  • Universal Inputs Accept LVDS, LVPECL, and LVCMOS
  • Selectable Clock Inputs Through Control Pin
  • 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 6-mm × 6-mm, 40-Pin VQFN (RHA)
  • ESD Protection Exceeds 3-kV HBM, 1-kV CDM
  • 2:12 Differential Buffer
  • Low Additive Jitter: < 300-fs RMS in
    10-kHz to 20-MHz
  • Low Output Skew of 35 ps (Maximum)
  • Universal Inputs Accept LVDS, LVPECL, and LVCMOS
  • Selectable Clock Inputs Through Control Pin
  • 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 6-mm × 6-mm, 40-Pin VQFN (RHA)
  • ESD Protection Exceeds 3-kV HBM, 1-kV CDM

The CDCLVD1212 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11) with minimum skew for clock distribution. The CDCLVD1212 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1212 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1212 is packaged in small, 40-pin, 6-mm × 6-mm VQFN package.

The CDCLVD1212 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11) with minimum skew for clock distribution. The CDCLVD1212 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1212 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1212 is packaged in small, 40-pin, 6-mm × 6-mm VQFN package.
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Technical documentation

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Type Title Date
* Data sheet CDCLVD1212 2:12 Low Additive Jitter LVDS Buffer datasheet (Rev. D) PDF | HTML 13 Nov 2017
User guide Low Additive Jitter, Twelve LVDS Outputs Clock Buffer Evaluation Board 01 Sep 2010

Design & development

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Simulation model

CDCLVD1212 IBIS Model (Rev. B)

SLLM091B.ZIP (15 KB) - IBIS Model
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