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CDCLVP1208

ACTIVE

Low jitter, 2-input selectable 1:8 universal-to-LVPECL buffer

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Data sheet

CDCLVP1208

ACTIVE
Data sheet Order now

Product details

Function Differential Additive RMS jitter (typ) (fs) 57 Output frequency (max) (MHz) 2000 Number of outputs 8 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 20 Features 2:8 fanout Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
Function Differential Additive RMS jitter (typ) (fs) 57 Output frequency (max) (MHz) 2000 Number of outputs 8 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 20 Features 2:8 fanout Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
VQFN (RHD) 28 25 mm² 5 x 5
  • 2:8 Differential Buffer
  • Selectable Clock Inputs Through Control terminal
  • Universal Inputs Accept LVPECL, LVDS, and
    LVCMOS/LVTTL
  • Eight LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 73 mA
  • Very Low Additive Jitter: <100 fs,rms in 10 kHz to
    20 MHz Offset Range:
    • 57 fs, rms (typical) at 122.88 MHz
    • 48 fs, rms (typical) at 156.25 MHz
    • 30 fs, rms (typical) at 312.5 MHz
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum Output Skew: 20 ps
  • LVPECL Reference Voltage, VAC_REF, Available
    for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Supports 105°C PCB Temperature
    (Measured with a Thermal Pad)
  • ESD Protection Exceeds 2 kV (HBM)
  • Available in 5-mm × 5-mm QFN-28 (RHD)
    Package
  • 2:8 Differential Buffer
  • Selectable Clock Inputs Through Control terminal
  • Universal Inputs Accept LVPECL, LVDS, and
    LVCMOS/LVTTL
  • Eight LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 73 mA
  • Very Low Additive Jitter: <100 fs,rms in 10 kHz to
    20 MHz Offset Range:
    • 57 fs, rms (typical) at 122.88 MHz
    • 48 fs, rms (typical) at 156.25 MHz
    • 30 fs, rms (typical) at 312.5 MHz
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum Output Skew: 20 ps
  • LVPECL Reference Voltage, VAC_REF, Available
    for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Supports 105°C PCB Temperature
    (Measured with a Thermal Pad)
  • ESD Protection Exceeds 2 kV (HBM)
  • Available in 5-mm × 5-mm QFN-28 (RHD)
    Package

The CDCLVP1208 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1208 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1208 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. The CDCLVP1208 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1208 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1208 is packaged in a small 28-pin, 5-mm × 5-mm QFN package and is characterized for operation from –40°C to 85°C.

The CDCLVP1208 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1208 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1208 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. The CDCLVP1208 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1208 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1208 is packaged in a small 28-pin, 5-mm × 5-mm QFN package and is characterized for operation from –40°C to 85°C.
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* Data sheet CDCLVP1208 Eight LVPECL Output, High-Performance Clock 2:8 Buffer datasheet (Rev. E) PDF | HTML 23 Nov 2015
User guide CDCLVP1208 User's Guide 21 Oct 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCLVP1208EVM — CDCLVP1208 Evaluation Module

The CDCLVP1208 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock inputs, selectable through a control pin. The device also features on-chip bias generators that can provide the LVPECL (...)
User guide: PDF
Not available on TI.com
Simulation model

CDCLVPxxxx IBIS Model (Rev. B)

SLLM056B.ZIP (40 KB) - IBIS Model
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Design tool

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PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware

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Clock network synchronizers
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Hardware development
Evaluation board
LMK04832EVM — LMK04832 JESD204B Clock Jitter Cleaner/Clock Generator/Distribution Evaluation Module LMX2571EPEVM — LMX2571-EP evaluation module for 1.34-GHz, low-power, extreme-temperature RF synthesizer LMX2594PSEVM — LMX2594 evaluation module for 15-GHz RF synthesizer with multiple-device phase synchronization XMICR-3P-LMX2492 — LMX2492 X-MWblock evaluation modules XMICR-3P-LMX2572 — LMX2572 X-MWblock evaluation modules XMICR-3P-LMX2592 — LMX2592 X-MWblock evaluation modules XMICR-3P-LMX2594 — LMX2594 X-MWblock evaluation modules XMICR-3P-LMX2595 — LMX2595 X-MWblock evaluation modules
Software
Application software & framework
TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software
IDE, configuration, compiler or debugger
CODELOADER — CodeLoader Software for device register programming
Support software
LMX9830-SW — LMX9830 Application Notes, Software, and Tools LMX9838-SW — LMX9838 Application Notes, Software, and Tools
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