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SN74HC03

ACTIVE

4-ch, 2-input, 2-V to 6-V 5.2 mA drive strength NAND gate with open-drain outputs

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Data sheet

SN74HC03

ACTIVE
Data sheet Order now

Product details

Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 5.2 IOH (max) (mA) 0 Input type Standard CMOS Output type Open-drain Features High speed (tpd 10- 50ns) Data rate (max) (Mbps) 28 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 5.2 IOH (max) (mA) 0 Input type Standard CMOS Output type Open-drain Features High speed (tpd 10- 50ns) Data rate (max) (Mbps) 28 Rating Catalog Operating temperature range (°C) -40 to 85
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Wide Operating Voltage Range: 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 20-µA Maximum ICC
  • Typical tpd = 8 ns at 5 V
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA
  • Wide Operating Voltage Range: 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 20-µA Maximum ICC
  • Typical tpd = 8 ns at 5 V
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA

This device contains four independent 2-input NAND Gates with open-drain outputs. Each gate performs the Boolean function Y = A ● B in positive logic.

This device contains four independent 2-input NAND Gates with open-drain outputs. Each gate performs the Boolean function Y = A ● B in positive logic.
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Technical documentation

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Type Title Date
* Data sheet SNx4HC03 Quadruple 2-Input NAND Gates with Open-Drain Outputs datasheet (Rev. F) PDF | HTML 30 Apr 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74HC03 Behavioral SPICE Model

SCLM233.ZIP (6 KB) - PSpice Model
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Design guide: PDF
Schematic: PDF
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Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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