For modern radar system developers currently using an FPGA or ASIC to connect to high speed data converters, who need faster time to market with increased performance and significant reduction in cost, power, and size, this reference design includes the first widely available processor integrating a JESD204B interface and Digital Front End (DFE) processing. Connecting to the ADC14X250 and DAC38J84 provides an efficient solution for avionics and defense applications such radar, electronic warfare, compute platforms and transponders.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Download ready-to-use system files to speed your design process.
Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Files used for 3D models or 2D drawings of IC components
Files used for 3D models or 2D drawings of IC components
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | White paper | Optimizing Modern Radar Systems using Low- Latency, High-Performance FFT Coproce | Dec. 17, 2015 | |
| * | Design guide | Optimized Radar System Design Using a DSP+ARM SoC and ADC14X250 Design Guide | Dec. 08, 2015 | |
| Application note | 66AK2L06 JESD Attachment to ADC14X250/DAC38J84 (Rev. A) | Jun. 24, 2016 | ||
| Product overview | 66AK2L06 SoC Product Bulletin | Apr. 15, 2015 |
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.