Software
GUI for evaluation module (EVM)
TIDA-010131
Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers
TIDA-010131
Overview
Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and a clock subsystem. The clock subsystem provides low noise sampling clocks with precise delay adjustment to achieve lowest channel-to-channel skew and optimum system performance like signal-to-noise ratio (SNR), spurious free dynamic range (SFDR), IMD3, effective number of bits (ENOB), and so forth. This reference design demonstrates multichannel JESD204B clocks generation and system performance with AFE7444 EVMs. Channel-to-channel skew better than 10 ps achieved with 6 GSPS/3 GSPS DAC/ADC clocks up to 2.6-GHz radio frequencies and system performance like SNR and SFDR are comparable to the AFE7444 data sheet specifications.
Features
- JESD204B complaint clock solution for 8T8R RF sampling analog front end
- Digital functions synchronization across multiple RF AFE transceivers
- Low phase noise clock generation for 14-bit, RF sampling AFEs
- Fine phase delay adjustment in steps of approximately 500 fs to achieve phase synchronization across multiple devices
- Supports high-speed data converters and capture cards (AFE7444EVM, TSW14J56EVM, TSW14J57EVM)
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Design files & products
Design files
Download ready-to-use system files to speed your design process.
TIDUEK4.PDF (7788 K)
Reference design overview and verified performance test data
TIDRZ30.ZIP (2263 K)
Detailed schematic diagram for design layout and components
TIDRZ31.ZIP (314 K)
Complete listing of design components, reference designators, and manufacturers/part numbers
TIDRZ32.ZIP (882 K)
Detailed overview of design layout for component placement
TIDRZ34.ZIP (19873 K)
Files used for 3D models or 2D drawings of IC components
TIDCFB2.ZIP (2572 K)
Design file that contains information on physical board layer of design PCB
TIDRZ33.ZIP (8507 K)
PCB layer plot file used for generating PCB design layout
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Technical documentation
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| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | Multichannel RF transceiver clocking reference design for RADARs and wireless 5G | Feb. 27, 2019 |
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