SN74ACT534

Name: SN74ACT534
Brand: TI
SKU: SN74ACT534
Price: 0.346 USD

アクティブ

3 ステート出力、オクタル・エッジ・トリガ D タイプ・フリップ・フロップ

ご注文はこちら

データシート

document-pdfAcrobat SN54ACT534, SN74ACT534 データシート (Rev. C) (英語)

SN74ACT534

アクティブ

データシート

ご注文はこちら

製品詳細

Number of channels

8

Technology family

ACT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

90

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

40

Features

Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

ACT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

90

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

40

Features

Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

PDIP (N)

20

228.702 mm² 24.33 x 9.4

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SOP (NS)

20

98.28 mm² 12.6 x 7.8

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

4.5-V to 5.5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 10.5 ns at 5 V
Inputs Are TTL-Voltage Compatible
3-State Inverting Outputs Drive Bus Lines Directly
Full Parallel Access for Loading

4.5-V to 5.5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 10.5 ns at 5 V
Inputs Are TTL-Voltage Compatible
3-State Inverting Outputs Drive Bus Lines Directly
Full Parallel Access for Loading

These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q\ outputs are set to the complements of the logic levels set up at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q\ outputs are set to the complements of the logic levels set up at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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