CDC-CDCM7005-CALC
CDC7005/CDCM7005 PLL ループ帯域カリキュレータ
CDC-CDCM7005-CALC
概要
This tool helps to determine the right divider values (M, N & P) and to choose the filter type and components. This calculator will help to find out the appropriate loop bandwidth, phase margin, jitter peaking, etc. just varying the loop parameters like PFD frequency, filter components, Charge pump current, and VCO gain (Hz/V). This is a software package that lets the Engineers enter a piecewise-linear noise model for the VCO (VCXO) and the reference clock source to predict the PLL output phase noise and hence calculate the phase jitter.
特長
The lab view based tool can:
- Determine the PFD frequency automatically
- Calculate loop bandwidth, Phase margin and Jitter peaking
- Predict the PLL output Phase noise
- Calculate Phase Jitter (rms)
技術資料
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| 種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
|---|---|---|---|---|---|---|
| データシート | CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner データシート (Rev. G) | PDF | HTML | 2015/12/03 |