Software
IDE, configuration, compiler or debugger
TIDA-00432
Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems
TIDA-00432
Overview
This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown for each EVM. The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analyzed, showing synchronization within 50 ps without characterized cables or calibrated propagation delays.
Features
- Demonstrates a typical phased array radar sub-system by showing synchronization of JESD204B giga-sample ADCs
- The LMK04828 clocking solution used is described in detail
- Test results show synchronization within 50 ps without any characterization of cables or calibration of propagation delays
- Xilinx firmware development is discussed to offer a clear understanding of the requirements
- This sub-system is tested and includes example configuration files
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Design files & products
Design files
Download ready-to-use system files to speed your design process.
TIDU752.PDF (2321 K)
Reference design overview and verified performance test data
TIDRDI4.PDF (555 K)
Detailed schematic diagram for design layout and components
TIDRDI5.PDF (140 K)
Complete listing of design components, reference designators, and manufacturers/part numbers
TIDC978.ZIP (712 K)
Design file that contains information on physical board layer of design PCB
Products
Includes TI products in the design and potential alternatives.
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Technical documentation
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| Type | Title | Date | ||
|---|---|---|---|---|
| Design guide | Synchronization of JESD204B Giga-Sample ADCs | Jan. 20, 2015 |
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