This regulation topology is designed to increase the efficiency of a DC/DC buck converter by disabling the converter during light-load operation and providing a regulated output voltage with a low-Iq LDO. During no-load or light-load conditions, the LDO allows for low-noise, low-Iq output voltage regulation while the DC/DC is disabled. Once the load is engaged, the DC/DC converter can provide high efficiency at high load currents, thereby combining the benefits of both devices.
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Reference design overview and verified performance test data
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Design file that contains information on physical board layer of design PCB
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| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | Adding an LDO for Increased Standby Mode Efficiency Design Guide | Jul. 07, 2015 |
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