CDCLVP111EVM-CVAL

CDCLVP111-SP 1:10 LVPECL Clock Driver Evaluation Module

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The CDCLVP111-SP EVM allows testing and validation of the CDCLVP111 clock distribution buffer utilizing a ceramic Engineering Model (EM).

Distributes one of two differential input clocks to 10 differential LVPECL output clocks
Clock input selectable
Low output skew
Wide supply range

CDCLVP111-SP — 1:10 high speed clock buffer with selectable input clock driver

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Evaluation board

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	Type	Title		Date
*	EVM User's guide	CDCLVP111-SP Evaluation Module (CDCLVP111EVM-CVAL)		17 Nov 2016

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