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UCC21222-Q1

ACTIVE

Automotive 3.0kVrms, 4A/6A 2-channel isolated gate driver w/ disable, programmable deadtime, 8V UVLO

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NEW UCC21330-Q1 ACTIVE Automotive, 3kVRMS 4A/6A two-channel gate driver with disable logic and programmable deadtime Improved CMTI, faster VDD startup

Product details

Number of channels 2 Isolation rating Basic Withstand isolation voltage (VISO) (Vrms) 3000 Working isolation voltage (VIOWM) (Vrms) 990 Transient isolation voltage (VIOTM) (VPK) 4242 TI functional safety category Functional Safety-Capable Power switch IGBT, MOSFET Peak output current (A) 6 Features Disable, Programmable dead time Output VCC/VDD (max) (V) 18 Output VCC/VDD (min) (V) 9.2 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.025 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Automotive Bootstrap supply voltage (max) (V) 990 Rise time (ns) 5 Fall time (ns) 6 Undervoltage lockout (typ) (V) 8
Number of channels 2 Isolation rating Basic Withstand isolation voltage (VISO) (Vrms) 3000 Working isolation voltage (VIOWM) (Vrms) 990 Transient isolation voltage (VIOTM) (VPK) 4242 TI functional safety category Functional Safety-Capable Power switch IGBT, MOSFET Peak output current (A) 6 Features Disable, Programmable dead time Output VCC/VDD (max) (V) 18 Output VCC/VDD (min) (V) 9.2 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.025 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Automotive Bootstrap supply voltage (max) (V) 990 Rise time (ns) 5 Fall time (ns) 6 Undervoltage lockout (typ) (V) 8
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Universal: dual low-side, dual high-side or half-bridge driver
  • AEC Q100 qualified with:
    • Device temperature grade 1
    • Device HBM ESD classification level H2
    • Device CDM ESD classification level C4B
  • Junction temperature range –40°C to 150°C
  • 4A peak source, 6A peak sink output
  • Common-mode transient immunity (CMTI) greater than 125V/ns
  • Up to 25V VDD output drive supply
    • 8V VDD UVLO
  • Switching parameters:
    • 33ns typical propagation delay
    • 5ns maximum pulse-width distortion
    • 10µs maximum VDD power-up delay
  • UVLO protection for all power supplies
  • Fast disable for power sequencing
  • Universal: dual low-side, dual high-side or half-bridge driver
  • AEC Q100 qualified with:
    • Device temperature grade 1
    • Device HBM ESD classification level H2
    • Device CDM ESD classification level C4B
  • Junction temperature range –40°C to 150°C
  • 4A peak source, 6A peak sink output
  • Common-mode transient immunity (CMTI) greater than 125V/ns
  • Up to 25V VDD output drive supply
    • 8V VDD UVLO
  • Switching parameters:
    • 33ns typical propagation delay
    • 5ns maximum pulse-width distortion
    • 10µs maximum VDD power-up delay
  • UVLO protection for all power supplies
  • Fast disable for power sequencing

The UCC21222-Q1 device is an isolated dual channel gate driver with programmable dead time and a wide temperature range. This device exhibits consistent performance and robustness under extreme temperature conditions. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.

The UCC21222-Q1 device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. A 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.

The input side is isolated from the two output drivers by a 3.0kVRMS isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI).

Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include a disable feature to shut down both outputs simultaneously when DIS is set high, an integrated deglitch filter that rejects input transients shorter than 5ns, and negative voltage handling for up to –2V spikes for 200ns on input and output pins. All supplies have UVLO protection.

The UCC21222-Q1 device is an isolated dual channel gate driver with programmable dead time and a wide temperature range. This device exhibits consistent performance and robustness under extreme temperature conditions. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.

The UCC21222-Q1 device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. A 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.

The input side is isolated from the two output drivers by a 3.0kVRMS isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI).

Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include a disable feature to shut down both outputs simultaneously when DIS is set high, an integrated deglitch filter that rejects input transients shorter than 5ns, and negative voltage handling for up to –2V spikes for 200ns on input and output pins. All supplies have UVLO protection.

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Technical documentation

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Type Title Date
* Data sheet UCC21222-Q1 Automotive 4A, 6A, 3kVRMS Isolated Dual-Channel Gate Driver with Dead Time datasheet (Rev. B) PDF | HTML 02 Apr 2024
White paper 신뢰할 수 있는 합리적 가격대의 절연 기술 개발과 관련한 고전압 설계 문제의 해결 (Rev. C) PDF | HTML 16 May 2024
White paper 以可靠且經濟實惠的隔離技術解決高電壓設計挑戰 (Rev. C) PDF | HTML 07 Mar 2024
Certificate VDE Certificate for Basic Isolation for DIN EN IEC 60747-17 (Rev. W) 31 Jan 2024
Application note Impact of Narrow Pulse Widths in Gate Driver Circuits (Rev. A) PDF | HTML 25 Jan 2024
White paper Addressing High-Volt Design Challenges w/ Reliable and Affordable Isolation Tech (Rev. C) PDF | HTML 26 Sep 2023
Certificate UCC21220 CQC Certificate of Product Certification 16 Aug 2023
Application brief The Use and Benefits of Ferrite Beads in Gate Drive Circuits PDF | HTML 16 Dec 2021
Application brief External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
Certificate UL Certification E181974 Vol 4. Sec 9 (Rev. A) 22 Jul 2019
User guide Gate Drive Voltage vs. Efficiency 25 Apr 2019
White paper Driving the future of HEV/EV with high-voltage solutions (Rev. B) 16 May 2018
Application note Isolation Glossary (Rev. A) 19 Sep 2017
Technical article Are you on-board? Demystifying EV charging systems PDF | HTML 31 Jul 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

UCC21220EVM-009 — UCC21220 4-A, 6-A 3.0-kVRMS Isolated Dual-Channel Gate Driver Evaluation Module

UCC21220EVM-009 is designed for evaluating UCC21220, which is a 3.0-kVRMS Isolated Dual-Channel Gate Driver with 4.0-A source and 6.0-A sink peak current capability. This EVM could be served to evaluate the driver IC against its datsheet. The EVM can also be used as Driver IC component selection (...)
User guide: PDF
Not available on TI.com
Simulation model

UCC21222-Q1 PSpice Transient Model

SLUM622.ZIP (57 KB) - PSpice Model
Simulation model

UCC21222-Q1 Unencrypted PSpice Transient Model

SLUM623.ZIP (3 KB) - PSpice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

PMP22650 — GaN-based, 6.6-kW, bidirectional, onboard charger reference design

The PMP22650 reference design is a 6.6-kW, bidirectional, onboard charger. The design employs a two-phase totem pole PFC and a full-bridge CLLLC converter with synchronous rectification. The CLLLC utilizes both frequency and phase modulation to regulate the output across the required regulation (...)
Test report: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 16 Ultra Librarian

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