The UC1825A-SP PWM controller is a radiation hardened version of the standard UC1825
family. Performance enhancements have been made to several of the circuit blocks. Error amplifier
gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current limit threshold is
assured to a tolerance of 5%. Oscillator discharge current is specified at 10 mA for accurate dead
time control. Frequency accuracy is improved to 6%. Start-up supply current, typically 100 µA, is ideal for offline applications. The output drivers are redesigned to actively sink
current during UVLO at no expense to the start-up current specification. In addition each output is
capable of 2-A peak currents during transitions.
Functional improvements have also been implemented in this device family. The UC1825
shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2 V. The
overcurrent comparator sets a latch that ensures full discharge of the soft-start capacitor before
allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of
continuous faults, the soft-start capacitor is fully charged before discharge to insure that the
fault frequency does not exceed the designed soft start period. The UC1825 CLOCK pin has become
CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and
has been buffered for easier interfacing.
The UC1825A-SP has dual alternating outputs and the same pin configuration of the UC1825.
The UC1825A-SP version parts have UVLO thresholds identical to the original UC1825.
The UC1825A-SP PWM controller is a radiation hardened version of the standard UC1825
family. Performance enhancements have been made to several of the circuit blocks. Error amplifier
gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current limit threshold is
assured to a tolerance of 5%. Oscillator discharge current is specified at 10 mA for accurate dead
time control. Frequency accuracy is improved to 6%. Start-up supply current, typically 100 µA, is ideal for offline applications. The output drivers are redesigned to actively sink
current during UVLO at no expense to the start-up current specification. In addition each output is
capable of 2-A peak currents during transitions.
Functional improvements have also been implemented in this device family. The UC1825
shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2 V. The
overcurrent comparator sets a latch that ensures full discharge of the soft-start capacitor before
allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of
continuous faults, the soft-start capacitor is fully charged before discharge to insure that the
fault frequency does not exceed the designed soft start period. The UC1825 CLOCK pin has become
CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and
has been buffered for easier interfacing.
The UC1825A-SP has dual alternating outputs and the same pin configuration of the UC1825.
The UC1825A-SP version parts have UVLO thresholds identical to the original UC1825.