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TPD2EUSB30

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Dual 0.7-pF, 5.5-V ±8-kV ESD protection diode with 5-A surge rating for USB 3.0

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Data sheet

TPD2EUSB30

ACTIVE
Data sheet Order now

Product details

Package name SOT-9X3 Peak pulse power (8/20 μs) (max) (W) 45 Vrwm (V) 5.5 Bi-/uni-directional Uni-Directional Number of channels 2 IO capacitance (typ) (pF) 0.7 IEC 61000-4-2 contact (±V) 8000 IEC 61000-4-5 (A) 5 Clamping voltage (V) 8 Dynamic resistance (typ) 0.6 Interface type USB 3.0 Breakdown voltage (min) (V) 7 IO leakage current (max) (nA) 100 Rating Catalog Operating temperature range (°C) -40 to 85
Package name SOT-9X3 Peak pulse power (8/20 μs) (max) (W) 45 Vrwm (V) 5.5 Bi-/uni-directional Uni-Directional Number of channels 2 IO capacitance (typ) (pF) 0.7 IEC 61000-4-2 contact (±V) 8000 IEC 61000-4-5 (A) 5 Clamping voltage (V) 8 Dynamic resistance (typ) 0.6 Interface type USB 3.0 Breakdown voltage (min) (V) 7 IO leakage current (max) (nA) 100 Rating Catalog Operating temperature range (°C) -40 to 85
SOT-9X3 (DRT) 3 1 mm² 1 x 1
  • Supports USB 3.0 data rates (5 Gbps)
  • IEC 61000-4-2 ESD protection (level 4 contact)
  • IEC 61000-4-5 surge protection
    • 5 A (8/20 µs)
  • Low capacitance
    • DRT: 0.7 pF (typical)
    • DQA: 0.8 pF (typical)
  • Dynamic resistance: 0.6 Ω (typical)
  • Space-saving DRT, DQA packages
  • Flow-through pin mapping
  • Supports USB 3.0 data rates (5 Gbps)
  • IEC 61000-4-2 ESD protection (level 4 contact)
  • IEC 61000-4-5 surge protection
    • 5 A (8/20 µs)
  • Low capacitance
    • DRT: 0.7 pF (typical)
    • DQA: 0.8 pF (typical)
  • Dynamic resistance: 0.6 Ω (typical)
  • Space-saving DRT, DQA packages
  • Flow-through pin mapping

The TPD2EUSB30, TPD2EUSB30A, and TPD4EUSB30 are 2 and 4 channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode arrays. The TPDxEUSB30/A devices are rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Contact). These devices also offer 5 A (8/20 µs) peak pulse current ratings per IEC 61000-4-5 (Surge) specification.

The TPD2EUSB30A offers low 4.5-V DC break-down voltage. The low capacitance, low break-down voltage, and low dynamic resistance make the TPD2EUSB30A a superior protection device for high-speed differential IOs.

The TPD2EUSB30 and TPD2EUSB30A are offered in space saving DRT (1 mm × 1 mm) package. The TPD4EUSB30 is offered in space saving DQA (2.5 mm × 1.0 mm) package.

The TPD2EUSB30, TPD2EUSB30A, and TPD4EUSB30 are 2 and 4 channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode arrays. The TPDxEUSB30/A devices are rated to dissipate ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Contact). These devices also offer 5 A (8/20 µs) peak pulse current ratings per IEC 61000-4-5 (Surge) specification.

The TPD2EUSB30A offers low 4.5-V DC break-down voltage. The low capacitance, low break-down voltage, and low dynamic resistance make the TPD2EUSB30A a superior protection device for high-speed differential IOs.

The TPD2EUSB30 and TPD2EUSB30A are offered in space saving DRT (1 mm × 1 mm) package. The TPD4EUSB30 is offered in space saving DQA (2.5 mm × 1.0 mm) package.
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Type Title Date
* Data sheet TPDxEUSB30 2-, 4-Channel ESD Protection for Super-Speed USB 3.0 Interface datasheet (Rev. G) PDF | HTML 01 Jun 2021
Application note ESD and Surge Protection for USB Interfaces (Rev. B) PDF | HTML 11 Jan 2024
User guide Reading and Understanding an ESD Protection Data Sheet (Rev. A) PDF | HTML 19 Sep 2023
Application note Capacitance Requirements for High Speed Signals (Rev. A) PDF | HTML 21 Aug 2023
Selection guide System-Level ESD Protection Guide (Rev. D) 07 Sep 2022
Application note ESD Packaging and Layout Guide (Rev. B) PDF | HTML 18 Aug 2022
Application note ESD Protection Layout Guide (Rev. A) PDF | HTML 07 Apr 2022
User guide Generic ESD Evaluation Module User's Guide (Rev. A) PDF | HTML 27 Sep 2021
White paper Designing USB for short-to-battery tolerance in automotive environments 10 Feb 2016
Analog Design Journal Design Considerations for System-Level ESD Circuit Protection 25 Sep 2012

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