TMS320DM355

Name: TMS320DM355
Brand: TI
SKU: TMS320DM355
Price: 17.103 USD

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Digital Media System-on-Chip (DMSoC)

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Data sheet

document-pdfAcrobat TMS320DM355 Digital Media System-on-Chip (DMSoC) datasheet (Rev. G)

Errata

document-pdfAcrobat
TMS320DM355 Digital Media System-on-Chip Silicon Errata (Revs 1.1, 1.3 and 1.4) (Rev. E)

TMS320DM355

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Data sheet

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Product details

DSP type

0

Operating system

Integrity, Linux, Neutrino, PrOS, Windows Embedded CE

Rating

Catalog

Operating temperature range (°C)

-40 to 100

DSP type

0

Operating system

Integrity, Linux, Neutrino, PrOS, Windows Embedded CE

Rating

Catalog

Operating temperature range (°C)

-40 to 100

NFBGA (ZCE)

337

169 mm² 13 x 13

Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
High-Performance Digital Media System-on-Chip (DMSoC)
Up to 270-MHz ARM926EJ-S™ Clock Rate
MPEG4/JPEG Coprocessor Supports
- Up to 720p MPEG4 SP
- Up to 50M Pixels per Second JPEG
Video Processing Subsystem
- Hardware IPIPE for Real-Time Image Processing
- Up to 14-bit CCD/CMOS Digital Interface
- Histogram Module
- Resize Image 1/16x to 8x
- Hardware On-Screen Display
- Supports digital HDTV (720p/1080i) output for connection to external encoder
Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs
Configurable Power-Saving Modes
On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
Extended Temperature 135- and 216-MHz Devices are Available
3.3-V and 1.8-V I/O, 1.3-V Core
Debug Interface Support
337-Pin Ball Grid Array at 65 nm Process Technology
High-Performance Digital Media System-on-Chip
- 135-, 216-, and 270-MHz ARM926EJ-S Clock Rate
- Fully Software-Compatible With ARM9
- Extended Temperature support for 135- and 216-Mhz Devices are Available
ARM926EJ-S Core
- Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
- DSP Instruction Extensions and Single Cycle MAC
- ARM® Jazelle® Technology
- EmbeddedICE-RT™ Logic for Real-Time Debug
ARM9 Memory Architecture
- 16K-Byte Instruction Cache
- 8K-Byte Data Cache
- 32K-Byte RAM
- 8K-Byte ROM
- Little Endian
MPEG4/JPEG Coprocessor
- Fixed Function Coprocessor Supports:
  - MPEG4 SP Codec at HD (720p), D1, VGA, SIF
  - JPEG Codec up to 50M Pixels per Second
Video Processing Subsystem
- Front End Provides:
  - Hardware IPIPE for Real-Time Processing
  - up to 14-bit CCD/CMOS Digital Interface
  - 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
  - 10-/8-bit CCIR6565/BT655 Interface
  - Up to 75-MHz Pixel Clock
  - Histogram Module
  - Resize Engine
    - Resize Images From 1/16x to 8x
    - Separate Horizontal/Vertical Control
    - Two Simultaneous Output Paths
- Back End Provides:
  - Hardware On-Screen Display (OSD)
  - Composite NTSC/PAL video encoder output
  - 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
  - BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  - Supports digital HDTV (720p/1080i) output for connection to external encoder
External Memory Interfaces (EMIFs)
- DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
- Asynchronous16-/8-bit Wide EMIF (AEMIF)
  - Flash Memory Interfaces
    - NAND (8-/16-bit Wide Data)
    - OneNAND(16-bit Wide Data)
Flash Card Interfaces
- Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
- SmartMedia
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
USB Port with Integrated 2.0 High-Speed PHY that Supports
- USB 2.0 Full and High-Speed Device
- USB 2.0 Low, Full, and High-Speed Host
Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
One 64-Bit Watch Dog Timer
Three UARTs (One fast UART with RTS and CTS Flow Control)
Three Serial Port Interfaces (SPI) each with two Chip-Selects
One Master/Slave Inter-Integrated Circuit (I²C) Bus®
Two Audio Serial Port (ASP)
- I2S and TDM I2S
- AC97 Audio Codec Interface
- S/PDIF via Software
- Standard Voice Codec Interface (AIC12)
- SPI Protocol (Master Mode Only)
Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
Configurable Power-Saving Modes
Crystal or External Clock Input (typically 24 MHz or 36 MHz)
Flexible PLL Clock Generators
Debug Interface Support
- IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
- ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
- Device Revision ID Readable by ARM
337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
90nm Process Technology
3.3-V and 1.8-V I/O, 1.3-V Internal

Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.

Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
High-Performance Digital Media System-on-Chip (DMSoC)
Up to 270-MHz ARM926EJ-S™ Clock Rate
MPEG4/JPEG Coprocessor Supports
- Up to 720p MPEG4 SP
- Up to 50M Pixels per Second JPEG
Video Processing Subsystem
- Hardware IPIPE for Real-Time Image Processing
- Up to 14-bit CCD/CMOS Digital Interface
- Histogram Module
- Resize Image 1/16x to 8x
- Hardware On-Screen Display
- Supports digital HDTV (720p/1080i) output for connection to external encoder
Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs
Configurable Power-Saving Modes
On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
Extended Temperature 135- and 216-MHz Devices are Available
3.3-V and 1.8-V I/O, 1.3-V Core
Debug Interface Support
337-Pin Ball Grid Array at 65 nm Process Technology
High-Performance Digital Media System-on-Chip
- 135-, 216-, and 270-MHz ARM926EJ-S Clock Rate
- Fully Software-Compatible With ARM9
- Extended Temperature support for 135- and 216-Mhz Devices are Available
ARM926EJ-S Core
- Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
- DSP Instruction Extensions and Single Cycle MAC
- ARM® Jazelle® Technology
- EmbeddedICE-RT™ Logic for Real-Time Debug
ARM9 Memory Architecture
- 16K-Byte Instruction Cache
- 8K-Byte Data Cache
- 32K-Byte RAM
- 8K-Byte ROM
- Little Endian
MPEG4/JPEG Coprocessor
- Fixed Function Coprocessor Supports:
  - MPEG4 SP Codec at HD (720p), D1, VGA, SIF
  - JPEG Codec up to 50M Pixels per Second
Video Processing Subsystem
- Front End Provides:
  - Hardware IPIPE for Real-Time Processing
  - up to 14-bit CCD/CMOS Digital Interface
  - 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
  - 10-/8-bit CCIR6565/BT655 Interface
  - Up to 75-MHz Pixel Clock
  - Histogram Module
  - Resize Engine
    - Resize Images From 1/16x to 8x
    - Separate Horizontal/Vertical Control
    - Two Simultaneous Output Paths
- Back End Provides:
  - Hardware On-Screen Display (OSD)
  - Composite NTSC/PAL video encoder output
  - 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
  - BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  - Supports digital HDTV (720p/1080i) output for connection to external encoder
External Memory Interfaces (EMIFs)
- DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
- Asynchronous16-/8-bit Wide EMIF (AEMIF)
  - Flash Memory Interfaces
    - NAND (8-/16-bit Wide Data)
    - OneNAND(16-bit Wide Data)
Flash Card Interfaces
- Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
- SmartMedia
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
USB Port with Integrated 2.0 High-Speed PHY that Supports
- USB 2.0 Full and High-Speed Device
- USB 2.0 Low, Full, and High-Speed Host
Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
One 64-Bit Watch Dog Timer
Three UARTs (One fast UART with RTS and CTS Flow Control)
Three Serial Port Interfaces (SPI) each with two Chip-Selects
One Master/Slave Inter-Integrated Circuit (I²C) Bus®
Two Audio Serial Port (ASP)
- I2S and TDM I2S
- AC97 Audio Codec Interface
- S/PDIF via Software
- Standard Voice Codec Interface (AIC12)
- SPI Protocol (Master Mode Only)
Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
Configurable Power-Saving Modes
Crystal or External Clock Input (typically 24 MHz or 36 MHz)
Flexible PLL Clock Generators
Debug Interface Support
- IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
- ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
- Device Revision ID Readable by ARM
337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
90nm Process Technology
3.3-V and 1.8-V I/O, 1.3-V Internal

Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.

The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications. Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with high picture quality, the DM355 combines high performance MPEG4 HD (720p) codecs and JPEG codecs up to 50M pixels per second, high quality, and low power consumption at a very low price point. The DM355 also enables seamless interface to most additional external devices required for a complete digital camera implementation. The interface is flexible enough to support various types of CCD and CMOS sensors, signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris and auto-focus motor controls, etc.

The DM355 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:

A coprocessor 15 (CP15) and protection module
Data and program Memory Management Units (MMUs) with table look-aside buffers.
Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

DM355 performance is enhanced by its MPEG4/JPEG coprocessor. The MPEG4/JPEG coprocessor performs the computational operations required for image processing; JPEG compression and MPEG4 video and imaging standard. The MPEG4/JPEG coprocessor supports MPEG4 SP at HD (720p), D1, VGA, SIF encode/decode resolutions and JPEG encode/decode up to 50M pixels per second.

The DM355 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:

A Video Processing Front-End (VPFE)
A Video Processing Back-End (VPBE)

The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM355 peripheral set includes:

An inter-integrated circuit (I2C) Bus interface
Two audio serial ports (ASP)
Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
A 64-bit watchdog timer
Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals
Three UARTs with hardware handshaking support on one UART
Three serial port Interfaces (SPI)
Four pulse width modulator (PWM) peripherals
Four real time out (RTO) outputs
Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
A USB 2.0 full and high-speed device and host interface
Two external memory interfaces:
- An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND.
- A high speed synchronous memory interface for DDR2/mDDR.

For software development support the DM355 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications. Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with high picture quality, the DM355 combines high performance MPEG4 HD (720p) codecs and JPEG codecs up to 50M pixels per second, high quality, and low power consumption at a very low price point. The DM355 also enables seamless interface to most additional external devices required for a complete digital camera implementation. The interface is flexible enough to support various types of CCD and CMOS sensors, signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris and auto-focus motor controls, etc.

The DM355 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:

A coprocessor 15 (CP15) and protection module
Data and program Memory Management Units (MMUs) with table look-aside buffers.
Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

DM355 performance is enhanced by its MPEG4/JPEG coprocessor. The MPEG4/JPEG coprocessor performs the computational operations required for image processing; JPEG compression and MPEG4 video and imaging standard. The MPEG4/JPEG coprocessor supports MPEG4 SP at HD (720p), D1, VGA, SIF encode/decode resolutions and JPEG encode/decode up to 50M pixels per second.

The DM355 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:

A Video Processing Front-End (VPFE)
A Video Processing Back-End (VPBE)

The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM355 peripheral set includes:

An inter-integrated circuit (I2C) Bus interface
Two audio serial ports (ASP)
Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
A 64-bit watchdog timer
Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals
Three UARTs with hardware handshaking support on one UART
Three serial port Interfaces (SPI)
Four pulse width modulator (PWM) peripherals
Four real time out (RTO) outputs
Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
A USB 2.0 full and high-speed device and host interface
Two external memory interfaces:
- An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND.
- A high speed synchronous memory interface for DDR2/mDDR.

For software development support the DM355 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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Technical documentation

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	Type	Title		Date
*	Data sheet	TMS320DM355 Digital Media System-on-Chip (DMSoC) datasheet (Rev. G)		24 Jun 2010
*	Errata	TMS320DM355 Digital Media System-on-Chip Silicon Errata (Revs 1.1, 1.3 and 1.4) (Rev. E)		24 Jun 2010
	Application note	High-Speed Interface Layout Guidelines (Rev. J)	PDF \| HTML	24 Feb 2023
	User guide	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)		01 Jun 2020
	Application note	Powering the TMS320DM335 and TMS320DM355 with the TPS650061		13 Oct 2011
	Application note	Migrating From TMS320DM35x to TMS320DM36x Devices (Rev. A)		02 Jun 2011
	Product overview	Multi-Megapixel Reference Designs (Rev. A)		22 Mar 2011
	Application note	Migrating From TMS320DM355/335 Silicon Revision 1.1 to 1.3 or 1.4 (Rev. B)		05 Jan 2011
	User guide	TMS320DM35x DMSoC Pulse-Width Modulator (PWM) User's Guide (Rev. B)		25 Aug 2010
	User guide	TMS320DM355 Digital Media System-on-Chip ARM Subsystem Reference Guide (Rev. A)		04 Aug 2010
	Application note	TMS320DM355 Power Consumption for Common Application Usage Scenarios (Rev. A)		16 Jul 2010
	More literature	TMS320DM3x DaVinci Video Processors		11 Apr 2010
	Application note	USB Compliance Checklist (Rev. A)		10 Mar 2010
	Application note	Implementing DDR2/mDDR PCB Layout on the TMS320DM35x DMSoC (Rev. D)		11 Nov 2009
	Application note	LSP 2.10 DaVinci Linux Drivers (Rev. A)		08 Jul 2009
	More literature	TMS320DM3x Highlights		03 Mar 2009
	More literature	Complimentary Analog Devices for DM355 Digital Media Processor		17 Feb 2009
	User guide	TMS320DM355 DVEVM v1.30 Getting Started Guide (Rev. B)		31 Dec 2008
	User guide	TMS320DM35x Digital Media System-on-Chip Video Processing Back End (VPBE) RG (Rev. C)		16 Oct 2008
	More literature	DaVinci Technology Overview Brochure (Rev. B)		27 Sep 2008
	Application note	Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A)		21 Aug 2008
	Application note	TMS320DM355 DSP Power Reference Design PR742 (Rev. A)		08 Aug 2008
	Application note	Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A)		17 Jul 2008
	User guide	TMS320DM35x Digital Media System-on-Chip Video Processing Front End (VPFE) RG (Rev. A)		30 Jun 2008
	Application note	Building a Small Embedded Linux Kernel Example (Rev. A)		27 May 2008
	User guide	TMS320DM35x DMSoC General-Purpose Input/Output (GPIO) User's Guide (Rev. B)		18 Mar 2008
	User guide	TMS320DM35x DMSoC Universal Serial Bus (USB) User's Guide (Rev. C)		13 Mar 2008
	User guide	TMS320DM355 DMSoC Peripherals Overview Reference Guide (Rev. A)		07 Dec 2007
	User guide	TMS320DM35x DMSoC Multimedia Card(MMC)/Secure Digital(SD)(SDIO) Card Controller (Rev. C)		28 Nov 2007
	User guide	TMS320DM35x DMSoC DDR2/mDDR Memory Controller Reference Guide (Rev. D)		19 Nov 2007
	User guide	TMS320DM35x DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (Rev. B)		23 Oct 2007
	User guide	TMS320DM35x DMSoC Enhanced DMA (EDMA) User's Guide (Rev. A)		23 Oct 2007
	User guide	TMS320DM35x DMSoC Serial Peripheral Interface (SPI) User's Guide (Rev. B)		16 Oct 2007
	More literature	TMS320DM355 DaVinci FAQ (Rev. A)		27 Sep 2007
	User guide	TMS320DM35x Audio Serial Port (ASP) Reference Guide (Rev. C)		04 Sep 2007
	User guide	TMS320DM35x DMSoC Inter-Integrated Circuit (I2C) Module User's Guide (Rev. A)		04 Sep 2007
	User guide	TMS320DM35x DMSoC Timer/Watchdog Timer User's Guide (Rev. A)		04 Sep 2007
	User guide	TMS320DM35x DMSoC Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. B)		04 Sep 2007
	User guide	TMS320DM35x Digital Media System-on-Chip Real Time Out (RTO) Reference Guide		04 Sep 2007
	More literature	DaVinci Newsletter - Fall 2007 Issue (Rev. B)		14 Aug 2007

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices. The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2. It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

Not available on TI.com

Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com

Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com

Software development kit (SDK)

LINUXDVSDK-DV — Linux Digital Video Software Development Kits (DVSDK) v2x/v3x - DaVinci Digital Media Processors

Effective Oct 2010 - Linux DVSDK v4 has been released. For DaVinci™ devices not listed above, search TI.com for your device part number; This product page will have a link to your current DVSDK.

The Linux™ Digital Video Software Development Kits (DVSDKs) enable DaVinci system integrators to (...)

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Application software & framework

TMDMFP — Multimedia Framework Products (MFP) - Codec Engine, Framework Components and XDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

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Operating system (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)

From: Mentor Graphics Corporation

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