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SN74LV373A-Q1

ACTIVE

Automotive Catalog Octal Transparent D-Type Latches With 3-State Outputs

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Data sheet

SN74LV373A-Q1

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Automotive
Number of channels 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Automotive
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Qualified for automotive applications
  • V CC operation of 2 V to 5.5 V
  • Maximum tpd of 8.5 ns at 5 V
  • Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 3.3 V, TA = 25°C
  • Supports mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • Qualified for automotive applications
  • V CC operation of 2 V to 5.5 V
  • Maximum tpd of 8.5 ns at 5 V
  • Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 3.3 V, TA = 25°C
  • Supports mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV373A-Q1 device is an octal transparent D-type latch designed for 2 V to 5.5 V V CC operation. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

The SN74LV373A-Q1 device is an octal transparent D-type latch designed for 2 V to 5.5 V V CC operation. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

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Technical documentation

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Type Title Date
* Data sheet SN74LV373A-Q1 Octal Transparent D-Type Latch With 3-State Outputs datasheet (Rev. D) PDF | HTML 24 Mar 2023
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
More literature Automotive Logic Devices Brochure 27 Aug 2014

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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TSSOP (PW) 20 Ultra Librarian
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