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SN74LS594

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Serial-in shift registers with output latches

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Data sheet

SN74LS594

ACTIVE
Data sheet Order now

Product details

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 65000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 65000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4
  • 8-Bit Serial-In, Parallel-Out Shift Registers with Storage
  • Choice of Output Configurations:
    'LS594 . . . Buffered
    'LS599 . . . Open-Collector
  • Guaranteed Shift Frequeny:
    DC to 20 MHz
  • Independent Direct-Overriding Clears on Shift and Storage Registers
  • 8-Bit Serial-In, Parallel-Out Shift Registers with Storage
  • Choice of Output Configurations:
    'LS594 . . . Buffered
    'LS599 . . . Open-Collector
  • Guaranteed Shift Frequeny:
    DC to 20 MHz
  • Independent Direct-Overriding Clears on Shift and Storage Registers

These devices each contain an 8-bit D-type sorage register. The storage register has buffered ('LS594) or open-collector ('LS599) outputs. Separate clocks and direct-overriding clears are provided on both the shift and storage registers. A shift output (QH') is provided for cascading purposes.

Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one clock pulse ahead of the storage register.

These devices each contain an 8-bit D-type sorage register. The storage register has buffered ('LS594) or open-collector ('LS599) outputs. Separate clocks and direct-overriding clears are provided on both the shift and storage registers. A shift output (QH') is provided for cascading purposes.

Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one clock pulse ahead of the storage register.
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* Data sheet 8-Bit Shift Registers With Output Latches datasheet 01 Mar 1988

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