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SN74HC112

ACTIVE

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset

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Data sheet

SN74HC112

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type LVTTL/CMOS Output type Push-Pull Clock frequency (MHz) 24 Supply current (max) (µA) 40 IOL (max) (mA) 4 IOH (max) (mA) -4 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 2 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type LVTTL/CMOS Output type Push-Pull Clock frequency (MHz) 24 Supply current (max) (µA) 40 IOL (max) (mA) 4 IOH (max) (mA) -4 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -40 to 85 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6
  • Wide operating voltage range of 2V to 6V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 40µA max ICC
  • Typical tpd = 13ns
  • ±4mA output drive at 5V
  • Low input current of 1µA max
  • Wide operating voltage range of 2V to 6V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 40µA max ICC
  • Typical tpd = 13ns
  • ±4mA output drive at 5V
  • Low input current of 1µA max

The SNx4HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high.

The SNx4HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high.
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Technical documentation

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Type Title Date
* Data sheet SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. I) PDF | HTML 16 Sep 2024
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note HCMOS Design Considerations (Rev. A) 09 Sep 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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Reference designs

TIDA-01171 — AC-Coupled RS-485 Reference Design

The TIDA-01171 reference design allows for RS-485 communication over an AC-coupled link, even at very low data rates.  This allows for nodes to communicate even when large ground potential differences exist between nodes.  Using AC coupling also helps to protect transceivers from bus (...)
Design guide: PDF
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PDIP (N) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
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