SN74CBTLV3861

Name: SN74CBTLV3861
Brand: TI
SKU: SN74CBTLV3861
Price: 0.242 USD

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3.3-V, 1:1 (SPST), 10-channel general-purpose FET bus switch with 1 control input

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Data sheet

document-pdfAcrobat SN74CBTLV3861 datasheet (Rev. H)

SN74CBTLV3861

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Data sheet

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Product details

Configuration

1:1 SPST

Number of channels

10

Power supply voltage - single (V)

2.5, 3.3

Protocols

Analog

Ron (typ) (Ω)

5

ON-state leakage current (max) (µA)

1

Bandwidth (MHz)

200

Operating temperature range (°C)

-40 to 85

Features

Powered-off protection

Input/output continuous current (max) (mA)

128

Rating

Catalog

Drain supply voltage (max) (V)

3.6

Supply voltage (max) (V)

3.6

Configuration

1:1 SPST

Number of channels

10

Power supply voltage - single (V)

2.5, 3.3

Protocols

Analog

Ron (typ) (Ω)

5

ON-state leakage current (max) (µA)

1

Bandwidth (MHz)

200

Operating temperature range (°C)

-40 to 85

Features

Powered-off protection

Input/output continuous current (max) (mA)

128

Rating

Catalog

Drain supply voltage (max) (V)

3.6

Supply voltage (max) (V)

3.6

SOIC (DW)

24

159.65 mm² 15.5 x 10.3

SOP (NS)

24

117 mm² 15 x 7.8

SSOP (DBQ)

24

51.9 mm² 8.65 x 6

TSSOP (PW)

24

49.92 mm² 7.8 x 6.4

TVSOP (DGV)

24

32 mm² 5 x 6.4

5- Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
I_off Supports Partial-Power-Down Mode Operation
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

5- Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
I_off Supports Partial-Power-Down Mode Operation
Flow-Through Architecture Optimizes PCB Layout
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

The SN74CBTLV3861 provides ten bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 10-bit bus switch. When output enable (OE\) is low, the 10-bit bus switch is on, and port A is connected to port B. When OE\ is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using I_off. The I_off feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3861 provides ten bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 10-bit bus switch. When output enable (OE\) is low, the 10-bit bus switch is on, and port A is connected to port B. When OE\ is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using I_off. The I_off feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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	Type	Title		Date
*	Data sheet	SN74CBTLV3861 datasheet (Rev. H)		10 Oct 2003
	Application note	Selecting the Correct Texas Instruments Signal Switch (Rev. E)	PDF \| HTML	02 Jun 2022
	Application note	Multiplexers and Signal Switches Glossary (Rev. B)	PDF \| HTML	01 Dec 2021
	Application brief	Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C)	PDF \| HTML	06 Jan 2021
	Selection guide	Little Logic Guide 2018 (Rev. G)		06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)		26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dec 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	More literature	Digital Bus Switch Selection Guide (Rev. A)		10 Nov 2004
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	User guide	Signal Switch Data Book (Rev. A)		14 Nov 2003
	Application note	Bus FET Switch Solutions for Live Insertion Applications		07 Feb 2003
	Application note	Texas Instruments Little Logic Application Report		01 Nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		13 Jun 2002
	User guide	CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B)		01 Dec 1998

Design & development

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Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.

User guide: PDF