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SN74AXC1T45-Q1

ACTIVE

Automotive single-bit dual-supply bus transceiver

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Data sheet

SN74AXC1T45-Q1

ACTIVE
Data sheet Order now

Product details

Technology family AXC Applications GPIO Bits (#) 1 High input voltage (min) (V) 0.455 High input voltage (max) (V) 3.6 Vout (min) (V) 0.65 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 12 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Automotive Operating temperature range (°C) -40 to 125
Technology family AXC Applications GPIO Bits (#) 1 High input voltage (min) (V) 0.455 High input voltage (max) (V) 3.6 Vout (min) (V) 0.65 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 12 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Automotive Operating temperature range (°C) -40 to 125
SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1
  • AEC-Q100 qualified for automotive applications
  • Fully configurable dual-rail design allows each port to operate with a power supply range from 0.65V to 3.6V
  • Operating temperature: –40°C to +125°C
  • Glitch-free power supply sequencing
  • Maximum quiescent current (ICCA + ICCB) of 10µA (85°C maximum) and 16µA (125°C maximum)
  • Up to 500Mbps support when translating from 1.8 to 3.3V
  • VCC isolation feature
    • If Either VCC input is below 100mV, all I/O outputs are disabled and become high-impedance
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000-V Human body model
    • 1000-V Charged-device model
  • AEC-Q100 qualified for automotive applications
  • Fully configurable dual-rail design allows each port to operate with a power supply range from 0.65V to 3.6V
  • Operating temperature: –40°C to +125°C
  • Glitch-free power supply sequencing
  • Maximum quiescent current (ICCA + ICCB) of 10µA (85°C maximum) and 16µA (125°C maximum)
  • Up to 500Mbps support when translating from 1.8 to 3.3V
  • VCC isolation feature
    • If Either VCC input is below 100mV, all I/O outputs are disabled and become high-impedance
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000-V Human body model
    • 1000-V Charged-device model

The SN74AXC1T45-Q1 is AEC-Q100 qualified single-bit non-inverting bus transceiver that uses two individually configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65V to 3.6V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65V to 3.6V. Additionally, the SN74AXC1T45-Q1 is compatible with a single-supply system.

The DIR pin determines the direction of signal propagation. With the DIR pin configured HIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B to Port A. The DIR pin is referenced to VCCA, meaning that its logic-high and logic-low thresholds track with VCCA.

This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry is designed so that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.

The VCC isolation feature is designed so that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling their outputs.

Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing robust power sequencing performance.

The SN74AXC1T45-Q1 is AEC-Q100 qualified single-bit non-inverting bus transceiver that uses two individually configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65V to 3.6V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65V to 3.6V. Additionally, the SN74AXC1T45-Q1 is compatible with a single-supply system.

The DIR pin determines the direction of signal propagation. With the DIR pin configured HIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B to Port A. The DIR pin is referenced to VCCA, meaning that its logic-high and logic-low thresholds track with VCCA.

This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry is designed so that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.

The VCC isolation feature is designed so that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling their outputs.

Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing robust power sequencing performance.
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Technical documentation

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* Data sheet SN74AXC1T45-Q1 Automotive Qualified Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation, Tri-State Outputs datasheet (Rev. D) PDF | HTML 31 Jan 2024
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 Oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024
Functional safety information SN74AXC1T45-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA PDF | HTML 13 Mar 2024
Application brief Future-Proofing Your Level Shifter Design with TI's Dual Footprint Packages PDF | HTML 05 Sep 2023
Application brief Translate Voltages for MDIO PDF | HTML 16 Jul 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Application note Translate Voltages for GPIO PDF | HTML 04 Aug 2020
Application note Glitch free power sequencing with AXC level translators (Rev. A) 20 Sep 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Evaluation board

AVCLVCDIRCNTRL-EVM — Generic EVM for Direction-Controlled Bidirectional Translation Device Supporting AVC and LVC

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

User guide: PDF
Not available on TI.com
Simulation model

SN74AXC1T45 IBIS Model (Rev. A)

SCEM581A.ZIP (51 KB) - IBIS Model
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Simulation model

SN74AXC1T45_Q1 IBIS Model

SCEM587.ZIP (49 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SOT-SC70 (DCK) 6 Ultra Librarian
USON (DRY) 6 Ultra Librarian
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