SN74AUC125

Name: SN74AUC125
Brand: TI
SKU: SN74AUC125
Price: 0.315 USD

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4-ch, 0.8-V to 2.7-V high speed buffers with 3-state outputs

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Data sheet

document-pdfAcrobat SN74AUC125 datasheet (Rev. A)

SN74AUC125

ACTIVE

Data sheet

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Product details

Technology family

AUC

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Number of channels

4

IOL (max) (mA)

9

Supply current (max) (µA)

10

IOH (max) (mA)

-9

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AUC

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Number of channels

4

IOL (max) (mA)

9

Supply current (max) (µA)

10

IOH (max) (mA)

-9

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

VQFN (RGY)

14

12.25 mm² 3.5 x 3.5

Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub-1-V Operable
Max t_pd of 2.1 ns at 1.8 V
Low Power Consumption, 10-µA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1500-V Charged-Device Model (C101)

Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub-1-V Operable
Max t_pd of 2.1 ns at 1.8 V
Low Power Consumption, 10-µA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1500-V Charged-Device Model (C101)

This quadruple bus buffer gate is designed for 0.8-V to 2.7-V V_CC operation, but is designed specifically for 1.6-V to 1.95-V V_CCoperation.

The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This quadruple bus buffer gate is designed for 0.8-V to 2.7-V V_CC operation, but is designed specifically for 1.6-V to 1.95-V V_CCoperation.

The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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	Type	Title	Date
*	Data sheet	SN74AUC125 datasheet (Rev. A)	28 Mar 2005
	Selection guide	Little Logic Guide 2018 (Rev. G)	06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)	26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dec 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	Product overview	Design Summary for WCSP Little Logic (Rev. B)	04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 Jun 2004
	User guide	Signal Switch Data Book (Rev. A)	14 Nov 2003
	Application note	Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices	21 Mar 2003
	User guide	AUC Data Book, January 2003 (Rev. A)	01 Jan 2003
	Application note	Texas Instruments Little Logic Application Report	01 Nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 Jun 2002
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS	27 Mar 2002
	More literature	AUC Product Brochure (Rev. A)	18 Mar 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

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