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SN74ALVCH162260

ACTIVE

12-Bit To 24-Bit Multiplexed D-Type Latch With 3-State Outputs

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Data sheet

SN74ALVCH162260

ACTIVE
Data sheet Order now

Product details

Number of channels 12 Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 40 Features Balanced outputs, Bus-hold, Damping resistors, Flow-through pinout, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 12 Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 40 Features Balanced outputs, Bus-hold, Damping resistors, Flow-through pinout, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DL) 56 190.647 mm² 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • B-Port Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Thin-Shrink Small-Outline (DGG) and Plastic Shrink Small-Outline (DL) Packages

NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • B-Port Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Thin-Shrink Small-Outline (DGG) and Plastic Shrink Small-Outline (DL) Packages

NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.

This 12-bit to 24-bit multiplexed D-type latch is designed for 1.65-V to 3.6-VCC operation.

The SN74ALVCH162260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory-interleaving applications.

Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B\, OE2B\, and OEA\) inputs control the bus transceiver functions. The OE1B\ and OE2B\ control signals also allow bank control in the A-to-B direction.

Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high.

The B outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162260 is characterized for operation from –40°C to 85°C.

This 12-bit to 24-bit multiplexed D-type latch is designed for 1.65-V to 3.6-VCC operation.

The SN74ALVCH162260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory-interleaving applications.

Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B\, OE2B\, and OEA\) inputs control the bus transceiver functions. The OE1B\ and OE2B\ control signals also allow bank control in the A-to-B direction.

Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high.

The B outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162260 is characterized for operation from –40°C to 85°C.
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Technical documentation

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Type Title Date
* Data sheet SN74ALVCH162260 datasheet (Rev. I) 05 Aug 2004
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 17 Sep 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 01 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 08 Sep 1999
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 03 Aug 1998
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 13 May 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

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Simulation model

SN74ALVCH162260 IBIS Model (Rev. B)

SCEM065B.ZIP (144 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SSOP (DL) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian
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