These 18-bit flip-flops feature 3-state outputs designed
specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing
wider buffer registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
The 'ABT16823 can be used as two 9-bit flip-flops or one 18-bit
flip-flop. With the clock-enable () input low, the D-type flip-flops enter data on the
low-to-high transitions of the clock. Taking high disables the clock buffer,
latching the outputs. Taking the clear () input low causes the Q outputs to
go low independently of the clock.
A buffered output-enable () input can be used to place the nine outputs in either
a normal logic state (high or low logic level) or a high-impedance
state. In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance state and
increased drive provide the capability to drive bus lines without
need for interface or pullup components.
does not affect
the internal operation of the flip-flops. Old data can be retained or
new data can be entered while the outputs are in the high-impedance
state.
When VCC is between 0 and 2.1 V, the device is in the
high-impedance state during power up or power down. However, to
ensure the high-impedance state above 2.1 V, should be tied to VCC
through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking/current-sourcing capability of the
driver.
The SN54ABT16823 is characterized for operation over the full
military temperature range of -55°C to 125°C. The
SN74ABT16823 is characterized for operation from -40°C to
85°C.
These 18-bit flip-flops feature 3-state outputs designed
specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing
wider buffer registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
The 'ABT16823 can be used as two 9-bit flip-flops or one 18-bit
flip-flop. With the clock-enable () input low, the D-type flip-flops enter data on the
low-to-high transitions of the clock. Taking high disables the clock buffer,
latching the outputs. Taking the clear () input low causes the Q outputs to
go low independently of the clock.
A buffered output-enable () input can be used to place the nine outputs in either
a normal logic state (high or low logic level) or a high-impedance
state. In the high-impedance state, the outputs neither load nor
drive the bus lines significantly. The high-impedance state and
increased drive provide the capability to drive bus lines without
need for interface or pullup components.
does not affect
the internal operation of the flip-flops. Old data can be retained or
new data can be entered while the outputs are in the high-impedance
state.
When VCC is between 0 and 2.1 V, the device is in the
high-impedance state during power up or power down. However, to
ensure the high-impedance state above 2.1 V, should be tied to VCC
through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking/current-sourcing capability of the
driver.
The SN54ABT16823 is characterized for operation over the full
military temperature range of -55°C to 125°C. The
SN74ABT16823 is characterized for operation from -40°C to
85°C.