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SN54AHCT123A

ACTIVE

DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

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Data sheet

SN54AHCT123A

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Technology family AHCT Input type TTL-Compatible CMOS Output type Push-Pull Supply current (µA) 40 IOL (max) (mA) 8 IOH (max) (mA) -8 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Retriggerable Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Technology family AHCT Input type TTL-Compatible CMOS Output type Push-Pull Supply current (µA) 40 IOL (max) (mA) 8 IOH (max) (mA) -8 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Retriggerable Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 CFP (W) 16 69.319 mm² 10.3 x 6.73 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Inputs are TTL-voltage compatible
  • Schmitt-trigger circuitry on A , B, and CLR inputs for slow input transition rates
  • Edge triggered from active-high or active-low gated logic inputs
  • Retriggerable for very long output pulses
  • Overriding clear terminates output pulse
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • Inputs are TTL-voltage compatible
  • Schmitt-trigger circuitry on A , B, and CLR inputs for slow input transition rates
  • Edge triggered from active-high or active-low gated logic inputs
  • Retriggerable for very long output pulses
  • Overriding clear terminates output pulse
  • Latch-up performance exceeds 100mA per JESD 78, class II

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
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Technical documentation

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Type Title Date
* Data sheet SNx4AHCT123A Dual Retriggerable Monostable Multivibrators datasheet (Rev. H) PDF | HTML 13 Jan 2025
* SMD SN54AHCT123A SMD 5962-98616 21 Jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application note Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) PDF | HTML 13 Mar 2020
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

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Package Pins CAD symbols, footprints & 3D models
CDIP (J) 16 Ultra Librarian
CFP (W) 16 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
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