DP83846A
Single 10/100 DsPHYTER Ethernet physical layer transceiver
DP83846A
- IEEE 802.3 ENDEC, 10BASE-T transceivers and filters
- IEEE 802.3u PCS, 100BASE-TX transceivers and filters
- IEEE 802.3 compliant Auto-Negotiation
- Output edge rate control eliminates external filtering for Transmit outputs
- BaseLine Wander compensation
- 5V/3.3V MAC interface
- IEEE 802.3u MII (16 pins/port)
- LED support (Link, Rx, Tx, Duplex, Speed, Collision)
- Single register access for complete PHY status
- 10/100 Mb/s packet loopback BIST (Built in Self Test)
- Low-power 3.3V, 0.35um CMOS technology
- Power consumption < 495mW (typical)
- 5V tolerant I/Os
- 80-pin LQFP package (12w) x (12l) x (1.4h) mm
The DP83846A is a full feature single Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols over Category 3 (10 Mb/s) or Category 5 Unsheilded twisted pair cables.
The DP83846A is designed for easy implementation of 10/100 Mb/s Ethernet home or office solutions. It interfaces to Twisted Pair media via an external transformer. This device interfaces directly to MAC devices through the IEEE 802.3u standard Media Independent Interface (MII) ensuring interoperability between products from different vendors.
The DP83846A utilizes on chip Digital Signal Processing (DSP) technology and digital Phase Lock Loops (PLLs) for robust performance under all operating conditions, enhanced noise immunity, and lower external component count when compared to analog solutions.
Technical documentation
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | DP83846A DsPHYTER - Single 10/100 Ethernet Transceiver datasheet (Rev. E) | 31 Aug 2011 |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
- Fab location
- Assembly location