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CD74HCT4066

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5-V, 1:1 (SPST), 4-channel analog switch with TTL inputs

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Data sheet

CD74HCT4066

ACTIVE
Data sheet Order now

Product details

Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 15 CON (typ) (pF) 5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -55 to 125 Input/output continuous current (max) (mA) 25 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
Configuration 1:1 SPST Number of channels 4 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 15 CON (typ) (pF) 5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (°C) -55 to 125 Input/output continuous current (max) (mA) 25 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6
  • Wide analog-input-voltage range: 0 V – 10 V
  • Low ON resistance:
    • VCC = 4.5 V: 25 Ω
    • VCC = 9 V: 15 Ω
  • Fast switching and propagation delay times
  • Low OFF leakage current
  • Wide operating temperature range: –55°C to 125°C
  • HC types:
    • 2 V to 10 V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V and 10 V
  • HCT types:
    • Direct LSTTL input logic compatibility, VIL= 0.8 V (maximum), VIH = 2 V (minimum)
    • CMOS input compatibility, Il ≤ 1 µA at VOL, VOH
  • Wide analog-input-voltage range: 0 V – 10 V
  • Low ON resistance:
    • VCC = 4.5 V: 25 Ω
    • VCC = 9 V: 15 Ω
  • Fast switching and propagation delay times
  • Low OFF leakage current
  • Wide operating temperature range: –55°C to 125°C
  • HC types:
    • 2 V to 10 V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V and 10 V
  • HCT types:
    • Direct LSTTL input logic compatibility, VIL= 0.8 V (maximum), VIH = 2 V (minimum)
    • CMOS input compatibility, Il ≤ 1 µA at VOL, VOH

The ’HC4066 and CD74HCT4066 devices contain four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

These switches feature the characteristic linear ON resistance of the metal-gate CD4066B device. Each switch is turned on by a high-level voltage on its control input.

The ’HC4066 and CD74HCT4066 devices contain four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

These switches feature the characteristic linear ON resistance of the metal-gate CD4066B device. Each switch is turned on by a high-level voltage on its control input.
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Technical documentation

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Type Title Date
* Data sheet High-Speed CMOS Logic Quad Bilateral Switch datasheet (Rev. E) PDF | HTML 16 Jul 2024
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02 Jun 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01 Dec 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

User guide: PDF
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Package Pins CAD symbols, footprints & 3D models
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
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