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ADC3569

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16-bit one-channel 500MSPS ADC with LVDS interface and up to 32768x decimation

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Data sheet

ADC3569

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 500 Resolution (Bits) 16 Number of input channels 1 Interface type DDR LVDS Features Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 413.1 Architecture Pipeline SNR (dB) 75.2 ENOB (Bits) 12.3 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500 Resolution (Bits) 16 Number of input channels 1 Interface type DDR LVDS Features Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 413.1 Architecture Pipeline SNR (dB) 75.2 ENOB (Bits) 12.3 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RTD) 64 81 mm² 9 x 9
  • 16-bit, single channel 250 and 500MSPS ADC
  • Noise spectral density: −160.4dBFS/Hz
  • Thermal Noise: 76.4dBFS
  • Single core (non-interleaved) ADC architecture
  • Power consumption:
    • 435mW (500MSPS)
    • 369mW (250MSPS)
  • Aperture jitter: 75fs
  • Buffered analog inputs
    • Programmable 100Ω and 200Ω termination
  • Input fullscale: 2VPP
  • Full power input bandwidth (−3dB): 1.4GHz
  • Spectral performance (fIN = 70MHz, −1dBFS):
    • SNR: 75.6dBFS
    • SFDR HD2,3: 80dBc
    • SFDR worst spur: 94dBFS
  • INL: ±2 LSB (typical)
  • DNL: ±0.5 LSB (typical)
  • Digital down-converters (DDCs)
    • Up to four independent DDCs
    • Complex and real decimation
    • Decimation: /2, /4 to /32768 decimation
    • 48-bit NCO phase coherent frequency hopping
  • Parallel/ Serial LVDS interface
    • 16-bit Parallel SDR, DDR LVDS for DDC bypass
    • Serial LVDS for decimation
    • 32-bit output option for high decimation
  • 16-bit, single channel 250 and 500MSPS ADC
  • Noise spectral density: −160.4dBFS/Hz
  • Thermal Noise: 76.4dBFS
  • Single core (non-interleaved) ADC architecture
  • Power consumption:
    • 435mW (500MSPS)
    • 369mW (250MSPS)
  • Aperture jitter: 75fs
  • Buffered analog inputs
    • Programmable 100Ω and 200Ω termination
  • Input fullscale: 2VPP
  • Full power input bandwidth (−3dB): 1.4GHz
  • Spectral performance (fIN = 70MHz, −1dBFS):
    • SNR: 75.6dBFS
    • SFDR HD2,3: 80dBc
    • SFDR worst spur: 94dBFS
  • INL: ±2 LSB (typical)
  • DNL: ±0.5 LSB (typical)
  • Digital down-converters (DDCs)
    • Up to four independent DDCs
    • Complex and real decimation
    • Decimation: /2, /4 to /32768 decimation
    • 48-bit NCO phase coherent frequency hopping
  • Parallel/ Serial LVDS interface
    • 16-bit Parallel SDR, DDR LVDS for DDC bypass
    • Serial LVDS for decimation
    • 32-bit output option for high decimation

The ADC3568 and ADC3569 (ADC356x) are 16-bit, 250MSPS and 500MSPS, single channel analog to digital converters (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -160dBFS/Hz (500MSPS).

The power efficient ADC architecture consumes 435mW at 500MSPS and provides power scaling with lower sampling rates (369mW at 250MSPS).

The ADC356x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC356x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a parallel SDR or DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation ratios, the output resolution can be increased to 32-bit.

The ADC3568 and ADC3569 (ADC356x) are 16-bit, 250MSPS and 500MSPS, single channel analog to digital converters (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -160dBFS/Hz (500MSPS).

The power efficient ADC architecture consumes 435mW at 500MSPS and provides power scaling with lower sampling rates (369mW at 250MSPS).

The ADC356x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC356x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a parallel SDR or DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation ratios, the output resolution can be increased to 32-bit.
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* Data sheet ADC3568, ADC3569 Single-Channel, 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet (Rev. A) PDF | HTML 21 Jan 2025

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ADC3669EVM — ADC3669 evaluation module

The ADC3669EVM is designed to evaluate the ADC3669 family of high-speed analog-to-digital converters (ADCs). The ADC3669EVM is populated with an ADC3669, a 16-bit dual-channel ADC with an LVDS interface that can operate at sample rates up to 500MSPS. The ADC3669EVM allows for evaluation of all (...)
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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