SLOSE35B March   2019  – July 2019 TX7316

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Simplified Block Diagram
      1.      Device Images
  4. 4Revision History
  5. 5Description (continued)
  6. 6Device and Documentation Support
    1. 6.1 Receiving Notification of Documentation Updates
    2. 6.2 Community Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Glossary
  7. 7Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCX|216
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Transmitter supports:
    • 16-channel 3-level or 8-channel 5-level pulser and active transmit/receive (T/R) switch
    • Very low power on-chip beamforming mode (5-level mode):
      • In receive-only mode: 17 mW
      • In transmit-receive mode: 598 mW
      • In CW mode (0.6-A mode): 1.97 W
      • In global power-down mode: 4.3 mW
  • 3-level, 5-level pulser:
    • Maximum output voltage: ±100 V
    • Minimum output voltage: ±1 V
    • Maximum output current: 2.4 A to 0.6 A
    • Maximum clamp current: 1 A to 0.25 A (in 3-level mode)
    • Maximum clamp current: 2 A to 0.5 A (in 5-level mode)
    • Second harmonic of –45 dBc at 5 MHz
    • CW mode jitter: 100 fs measured from 100 Hz to 20 kHz
    • CW mode close-in phase noise: –154 dBc/Hz at 1 kHz offset for 5 MHz signal
    • Supports 4.8-A mode in 5-level mode
    • –3-dB Bandwidth with 1-kΩ || 240-pF load
      • 20 MHz (For ±100-V supply in 2.4-A mode)
      • 36 MHz (For ±100-V supply in 4.8-A mode)
      • 25 MHz (For ±70-V supply in 2.4-A mode)
  • Active transmit/receive (T/R) switch with:
    • ON/OFF control signal
    • Turnon resistance of 12 Ω
    • Bandwidth: 50 MHz
    • HD2: -50 dBc
    • Turnon time: 0.5 μs
    • Turnoff time: 1.75 μs
    • Transient glitch: 50 mVPP
  • Off-chip beam former with:
    • Jitter cleaning using synchronization feature
    • Maximum synchronization clock frequency: 200 MHz
  • On-chip beam former with:
    • Delay resolution: one beamformer clock period, minimum 5 ns
    • Maximum delay: 213 beamformer clock period
    • Maximum beamformer clock speed: 200 MHz
    • On-chip RAM to store
      • 16 Delay profiles
      • 48/28 pattern-profiles for 3- or 5-level mode
  • High-speed (100 MHz maximum) 1.8-V and 2.5-V CMOS serial programming interface
  • Automatic thermal shutdown
  • No specific power sequencing requirement in 3-level mode
  • Small package: NFBGA-216 (15 mm × 10 mm) with 0.8-mm pitch