SLUSCE4A January   2017  – July 2017 TPS548B22

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 25-A FET
      2. 7.3.2 On-Resistance
      3. 7.3.3 Package Size, Efficiency and Thermal Performance
      4. 7.3.4 Soft-Start Operation
      5. 7.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
      6. 7.3.6 EN_UVLO Pin Functionality
      7. 7.3.7 Fault Protections
        1. 7.3.7.1 Current Limit (ILIM) Functionality
        2. 7.3.7.2 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
        3. 7.3.7.3 Out-of-Bounds Operation
        4. 7.3.7.4 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 DCAP3 Control Topology
      2. 7.4.2 DCAP Control Topology
    5. 7.5 Programming
      1. 7.5.1 Programmable Pin-Strap Settings
        1. 7.5.1.1 Frequency Selection (FSEL) Pin
        2. 7.5.1.2 VSEL Pin
        3. 7.5.1.3 DCAP3 Control and Mode Selection
        4. 7.5.1.4 Application Workaround to Support 4-ms and 8-ms SS Settings
      2. 7.5.2 Programmable Analog Configurations
        1. 7.5.2.1 RSP/RSN Remote Sensing Functionality
          1. 7.5.2.1.1 Output Differential Remote Sensing Amplifier
        2. 7.5.2.2 Power Good (PGOOD Pin) Functionality
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS548B22 1.5-V to 18-V Input, 1-V Output, 25-A Converter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Design Procedure
        1. 8.2.3.1  Switching Frequency Selection
        2. 8.2.3.2  Inductor Selection
        3. 8.2.3.3  Output Capacitor Selection
          1. 8.2.3.3.1 Minimum Output Capacitance to Ensure Stability
          2. 8.2.3.3.2 Response to a Load Transient
          3. 8.2.3.3.3 Output Voltage Ripple
        4. 8.2.3.4  Input Capacitor Selection
        5. 8.2.3.5  Bootstrap Capacitor Selection
        6. 8.2.3.6  BP Pin
        7. 8.2.3.7  R-C Snubber and VIN Pin High-Frequency Bypass
        8. 8.2.3.8  Optimize Reference Voltage (VSEL)
        9. 8.2.3.9  MODE Pin Selection
        10. 8.2.3.10 Overcurrent Limit Design.
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RVF|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Conversion Input Voltage Range (PVIN): 1.5 V to 18 V
  • Input Bias Voltage (VDD) Range: 4.5 V to 22 V
  • Output Voltage Range: 0.6 V to 5.5 V
  • Integrated, 4.1-mΩ and 1.9-mΩ Power MOSFETs With 25-A Continuous Output Current
  • Voltage Reference 0.6 V to 1.2 V in 50-mV Steps Using VSEL Pin
  • ±0.5%, 0.9-VREF Tolerance Range: –40°C to +125°C Junction Temperature
  • True Differential Remote Sense Amplifier
  • D-CAP3™ Control Loop to Support Large Bulk Capacitors and/or Small MLCCs Without External Compensation
  • Adaptive On-Time Control With 4 Selectable Frequency Settings: 425 kHz, 650 kHz, 875 kHz and 1.05 MHz
  • Temperature Compensated and with Programmable Positive and Negative Current Limit and OC Clamp
  • Choice of Hiccup or Latch-Off OVP or UVP
  • VDD UVLO External Adjustment by Precision EN Hysteresis
  • Prebias Start-up Support
  • Eco-Mode and FCCM Selectable
  • Full Suite of Fault Protection and PGOOD
  • 7 mm × 5 mm × 1.5 mm, 40-Pin, Stack Clipped LQFN-CLIP Package

2 Applications

  • Enterprise Storage, SSD, NAS
  • Wireless and Wired Communication Infrastructure
  • Industrial PCs, Automation, ATE, PLC, Video Surveillance
  • Enterprise Server, Switches, Routers
  • AISIC, SoC, FPGA, DSP Core and I/O Rails

3 Description

The TPS548B22 device is a compact single buck converter with adaptive on-time, D-CAP3 mode control. It is designed for high accuracy, high efficiency, fast transient response, ease-of-use, low external component count, and space-conscious power systems.

This device features full differential sense, TI integrated FETs with a high-side on-resistance of 4.1 mΩ and a low-side on-resistance of 1.9 mΩ. The device also features accurate 0.5%, 0.9-V reference with an ambient temperature range between –40°C and +125°C. Competitive features include: very low external component count, accurate load regulation and line regulation, output voltage setpoint accuracy, auto-skip or FCCM mode operation, and internal soft-start control.

The TPS548B22 device is available in 7 mm × 5 mm, 40-pin, LQFN-CLIP (RVF) package (RoHs exempt).

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS548B22 LQFN-CLIP (40) 7.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Application

TPS548B22 simp_app_slusce4.gif