SLUSDJ0A
November 2018 – December 2018
TPS546D24
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Simplified Application
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Device and Documentation Support
6.1
Device Support
6.1.1
Third-Party Products Disclaimer
6.1.2
Development Support
6.1.2.1
Custom Design With WEBENCH® Tools
6.1.2.2
Texas Instruments Fusion Digital Power Designer
6.2
Receiving Notification of Documentation Updates
6.3
Community Resources
6.4
Trademarks
6.5
Electrostatic Discharge Caution
6.6
Glossary
7
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RVF|40
MPQF268C
Thermal pad, mechanical data (Package|Pins)
RVF|40
QFND333E
Orderable Information
slusdj0a_oa
slusdj0a_pm
1
Features
Split Rail Support: 2.95-V to 16-V PVIN;
2.95-V to 18-V AVIN (4-V
IN
VDD5 for Switching)
Integrated 4.5-mΩ/0.9-mΩ MOSFETs
Average Current Mode Control With Selectable Internal Compensation
2×, 3x, 4× Stackable With Current Sharing up to 160 A, Supporting a Single Address per Output
Selectable 0.6-V to 5.5-V Output via Pin Strap or 0.25-V to 5.5-V via PMBus VOUT_COMMAND
Extensive PMBus Command Set With Telemetry for V
OUT
, I
OUT
and Internal Die Temperature
Differential Remote Sensing With Internal FB Divider for < 1% V
OUT
Error –40°C to +150°C T
J
AVS and Margining Capabilities Through PMBus
MSEL Pins Pin Programming PMBus Defaults
12 Selectable Switching Frequencies from 225
kHz to 1.5 MHz (8 Pin-Strap Options)
Frequency Sync In/Sync Out
Supports Prebiased Output
Supports Strongly Coupled Inductor
7 mm × 5 mm × 1.5 mm, 40-pin QFN,
Pitch = 0.5 mm
Create a Custom Design Using the TPS546D24 With
WEBENCH® Power Designer