SLUSB69B May   2014  – July 2016 TPS544B20 , TPS544C20

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Turn-On and Turn-Off Delay and Sequencing
      2. 8.3.2  Pre-Biased Output Start-Up
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Differential Remote Sense and Output Voltage Setting
      5. 8.3.5  PMBus Output Voltage Adjustment
      6. 8.3.6  Switching Frequency
      7. 8.3.7  Soft-Start
      8. 8.3.8  Linear Regulators BP3 and BP6
      9. 8.3.9  External Bypass (BPEXT)
      10. 8.3.10 Current Monitoring and Low-Side MOSFET Overcurrent Protection
      11. 8.3.11 High-Side MOSFET Short-Circuit Protection
      12. 8.3.12 Over-Temperature Protection
      13. 8.3.13 Input Undervoltage Lockout (UVLO)
      14. 8.3.14 Output Overvoltage and Undervoltage Protection
      15. 8.3.15 Fault Protection Responses
      16. 8.3.16 PMBus General Description
      17. 8.3.17 PMBus Address
      18. 8.3.18 PMBus Connections
      19. 8.3.19 Auto ARA (Alert Response Address) Response
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conduction Mode
      2. 8.4.2 Operation with Internal BP6 Regulator
      3. 8.4.3 Operation with BP External
      4. 8.4.4 Operation with CNTL Signal Control
      5. 8.4.5 Operation with OPERATION Control
      6. 8.4.6 Operation with CNTL and OPERATION Control
      7. 8.4.7 Operation with Output Margining
    5. 8.5 Programming
      1. 8.5.1 Supported PMBus Commands
    6. 8.6 Register Maps
      1. 8.6.1  OPERATION (01h)
        1. 8.6.1.1 On
        2. 8.6.1.2 Margin
      2. 8.6.2  ON_OFF_CONFIG (02h)
        1. 8.6.2.1 pu
        2. 8.6.2.2 cmd
        3. 8.6.2.3 cpr
        4. 8.6.2.4 pol
        5. 8.6.2.5 cpa
      3. 8.6.3  CLEAR_FAULTS (03h)
      4. 8.6.4  WRITE_PROTECT (10h)
        1. 8.6.4.1 bit5
        2. 8.6.4.2 bit6
        3. 8.6.4.3 bit7
      5. 8.6.5  STORE_USER_ALL (15h)
      6. 8.6.6  RESTORE_USER_ALL (16h)
      7. 8.6.7  CAPABILITY (19h)
      8. 8.6.8  VOUT_MODE (20h)
        1. 8.6.8.1 Mode:
        2. 8.6.8.2 Exponent
      9. 8.6.9  VIN_ON (35h)
        1. 8.6.9.1 Exponent
        2. 8.6.9.2 Mantissa
      10. 8.6.10 VIN_OFF (36h)
        1. 8.6.10.1 Exponent
        2. 8.6.10.2 Mantissa
      11. 8.6.11 IOUT_CAL_OFFSET (39h)
        1. 8.6.11.1 Exponent
        2. 8.6.11.2 Mantissa
      12. 8.6.12 IOUT_OC_FAULT_LIMIT (46h)
        1. 8.6.12.1 Exponent
        2. 8.6.12.2 Mantissa
      13. 8.6.13 IOUT_OC_FAULT_RESPONSE (47h)
        1. 8.6.13.1 RS[2:0]
      14. 8.6.14 IOUT_OC_WARN_LIMIT (4Ah)
        1. 8.6.14.1 Exponent
        2. 8.6.14.2 Mantissa
      15. 8.6.15 OT_FAULT_LIMIT (4Fh)
        1. 8.6.15.1 Exponent
        2. 8.6.15.2 Mantissa
      16. 8.6.16 OT_WARN_LIMIT (51h)
        1. 8.6.16.1 Exponent
        2. 8.6.16.2 Mantissa
      17. 8.6.17 TON_RISE (61h)
        1. 8.6.17.1 Exponent
        2. 8.6.17.2 Mantissa
      18. 8.6.18 STATUS_BYTE (78h)
      19. 8.6.19 STATUS_WORD (79h)
      20. 8.6.20 STATUS_VOUT (7Ah)
      21. 8.6.21 STATUS_IOUT (7Bh)
      22. 8.6.22 STATUS_TEMPERATURE (7Dh)
      23. 8.6.23 STATUS_CML (7Eh)
      24. 8.6.24 STATUS_MFR_SPECIFIC (80h)
      25. 8.6.25 READ_VOUT (8Bh)
      26. 8.6.26 READ_IOUT (8Ch)
        1. 8.6.26.1 Exponent
        2. 8.6.26.2 Mantissa
      27. 8.6.27 READ_TEMPERATURE_2 (8Eh)
        1. 8.6.27.1 Exponent
        2. 8.6.27.2 Mantissa
      28. 8.6.28 PMBUS_REVISION (98h)
      29. 8.6.29 MFR_SPECIFIC_00 (D0h)
      30. 8.6.30 VREF_TRIM (MFR_SPECIFIC_04) (D4h)
      31. 8.6.31 STEP_VREF_MARGIN_HIGH (MFR_SPECIFIC_05) (D5h)
      32. 8.6.32 STEP_VREF_MARGIN_LOW (MFR_SPECIFIC_06) (D6h)
      33. 8.6.33 PCT_VOUT_FAULT_PG_LIMIT (MFR_SPECIFIC_07) (D7h)
      34. 8.6.34 SEQUENCE_TON_TOFF_DELAY (MFR_SPECIFIC_08) (D8h)
      35. 8.6.35 OPTIONS (MFR_SPECIFIC_21) (E5h)
      36. 8.6.36 MASK_SMBALERT (MFR_SPECIFIC_23) (E7h)
        1. 8.6.36.1  mOTFI
        2. 8.6.36.2  mPRTCL
        3. 8.6.36.3  mSMBTO
        4. 8.6.36.4  mIVC
        5. 8.6.36.5  mIVD
        6. 8.6.36.6  mPEC
        7. 8.6.36.7  mMEM
        8. 8.6.36.8  Auto_ARA
        9. 8.6.36.9  mOTF
        10. 8.6.36.10 mOTW
        11. 8.6.36.11 mOCF
        12. 8.6.36.12 mOCW
        13. 8.6.36.13 mOVF
        14. 8.6.36.14 mUVF
        15. 8.6.36.15 mPGOOD
        16. 8.6.36.16 mVIN_UV
      37. 8.6.37 DEVICE_CODE (MFR_SPECIFIC_44) (FCh)
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency Selection
        2. 9.2.2.2  Inductor Selection
        3. 9.2.2.3  Output Capacitor Selection
          1. 9.2.2.3.1 Response to a Load Transition
          2. 9.2.2.3.2 Output Voltage Ripple
        4. 9.2.2.4  D-CAP Mode and D-CAP2 Mode Stability
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  Bootstrap Capacitor and Resistor Selection
        7. 9.2.2.7  BP6, BP3 and BPEXT
        8. 9.2.2.8  R-C Snubber and VIN Pin High-Frequency Bypass
        9. 9.2.2.9  Temperature Sensor
        10. 9.2.2.10 Key PMBus Parameter Selection
          1. 9.2.2.10.1 Enable, UVLO and Sequencing
          2. 9.2.2.10.2 Soft-Start Time
          3. 9.2.2.10.3 Overcurrent Threshold and Response
          4. 9.2.2.10.4 Power Good, Output Overvoltage and Undervoltage Protection
        11. 9.2.2.11 Output Voltage Setting and Frequency Compensation Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Mounting and Thermal Profile Recommendation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Texas Instruments Fusion Digital Power Designer
      2. 12.1.2 Device Nomenclature
    2. 12.2 Related Links
    3. 12.3 Trademarks
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • PMBus-Enabled Converters: 20 A, 30 A
  • 4.5-V to 18-V input, 0.6-V to 5.5-V Output
  • 5 mm × 7 mm LQFN Package with 0.5-mm Pitch
  • Single Thermal Pad
  • Integrated 4.5-mΩ and 2.0-mΩ Stacked NexFET™ Power Stage
  • 600-mV, 0.5% Reference
  • Lossless, Low-Side MOSFET Current Sensing
  • Selectable D-CAP™ and D-CAP2™ Mode Control
  • Differential Remote Sensing
  • Monotonic Start-Up into Pre-Biased Output
  • Output Voltage Margin and Trim
  • Output Voltage and Output Current Reporting
  • External Temperature Monitoring with 2N3904
  • Programmable via PMBus
    • Overcurrent Protection
    • UVLO, Soft-Start
    • PGOOD, OV, UV, OT Levels
    • Fault Responses
    • Turn-On and Turn-Off Delays
  • Thermal Shutdown
  • Pin Compatible 20-A, 30-A Converters

Applications

  • Test and Instrumentation
  • Ethernet Switches, Optical Switches, Routers, Base Stations
  • Servers
  • Enterprise Storage SSD
  • High-Density Power Solutions

Description

The TPS544B20 and TPS544C20 devices are PMBus compatible, non-isolated DC-DC Integrated FET converters, capable of high-frequency operation and delivering 20-A , or 30-A current output from a 5 mm × 7 mm package, enabling high-power density and fast transient performance with minimal PCB area. The PMBus interface provides for converter configuration as well as monitoring of key parameters including output voltage, current and an optional external temperature. High-frequency, low-loss switching, provided by an integrated NexFET power stage and optimized drivers, allows for very high-density power solutions and reduced inductor and filter capacitor sizes. Response to fault conditions can be set to either restart or latch off depending on system requirements.

Table 1. Device Information(1)

PART NAME PACKAGE BODY SIZE (NOM)
TPS544B20 LQFN (40) 5.00 mm × 7.00 mm
TPS544C20
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Efficiency vs Output Current

TPS544B20 TPS544C20 Efficiency_12vin_fp.png

Revision History

Changes from A Revision (February 2016) to B Revision

Changes from * Revision (May 2014) to A Revision