SBVS301B
October 2016 – September 2021
TPS3850
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Timing Diagrams
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagrams
7.3
Feature Description
7.3.1
CRST
7.3.2
RESET
7.3.3
Over- and Undervoltage Fault Detection
7.3.4
Adjustable Operation Using the TPS3850H01
7.3.5
Window Watchdog
7.3.5.1
SET0 and SET1
7.3.5.1.1
Enabling the Window Watchdog
7.3.5.1.2
Disabling the Watchdog Timer When Using the CRST Capacitor
7.3.5.1.3
SET0 and SET1 During Normal Watchdog Operation
7.3.6
Window Watchdog Timer
7.3.6.1
CWD
7.3.6.2
WDI Functionality
7.3.6.3
WDO Functionality
7.4
Device Functional Modes
7.4.1
VDD is Below VPOR ( VDD < VPOR)
7.4.2
Above Power-On-Reset But Less Than UVLO (VPOR ≤ VDD < VUVLO)
7.4.3
Above UVLO But Less Than VDD (min) (VUVLO ≤ VDD < VDD (min))
7.4.4
Normal Operation (VDD ≥ VDD (min))
8
Application and Implementation
8.1
Application Information
8.1.1
CRST Delay
8.1.1.1
Factory-Programmed Reset Delay Timing
8.1.1.2
Programmable Reset Delay-Timing
8.1.2
CWD Functionality
8.1.2.1
Factory-Programmed Timing Options
8.1.2.2
Adjustable Capacitor Timing
8.1.3
Adjustable SENSE Configuration
8.1.4
Overdrive on the SENSE Pin
8.2
Typical Applications
8.2.1
Design 1: Monitoring a 1.2-V Rail with Factory-Programmable Watchdog Timing
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Monitoring the 1.2-V Rail
8.2.1.2.2
Meeting the Minimum Reset Delay
8.2.1.2.3
Setting the Watchdog Window
8.2.1.2.4
Calculating the RESET and WDO Pullup Resistor
8.2.1.3
Application Curves
8.2.2
Design 2: Using TPS3850H01 to monitor a 0.7-V Rail With an Adjustable Window Watchdog Timing
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.2.1
Meeting the Minimum Reset Delay
8.2.2.2.2
Setting the Window Watchdog
8.2.2.2.3
Watchdog Disabled During the Initialization Period
8.2.2.2.4
Calculating the Sense Resistor
8.2.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Device Nomenclature
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
Support Resources
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DRC|10
MPDS117L
Thermal pad, mechanical data (Package|Pins)
DRC|10
QFND013N
Orderable Information
sbvs301b_oa
sbvs301b_pm
1
Features
Input voltage range: VDD = 1.6 V to 6.5 V
0.8% Voltage threshold accuracy
Low supply current: I
DD
= 10 µA (typical)
User-programmable watchdog timeout
User-programmable reset delay
Factory-programmed precision watchdog and reset timers
Open-drain outputs
Precision over- and undervoltage monitoring:
Supports common rails from 0.9 V to 5.0 V
±4% and ±7% Fault windows available
0.5% Hysteresis
Watchdog disable feature
Available in a small 3-mm × 3-mm, 10-Pin VSON package
Junction operating temperature range:
–40°C to +125°C