SLASEC6A April   2016  – November 2016 TPA3244

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Audio Characteristics (BTL)
    7. 7.7 Audio Characteristics (SE)
    8. 7.8 Audio Characteristics (PBTL)
    9. 7.9 Typical Characteristics
      1. 7.9.1 BTL Configuration
      2. 7.9.2 SE Configuration
      3. 7.9.3 PBTL Configuration
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Error Reporting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Protection System
        1. 9.4.1.1 Overload and Short Circuit Current Protection
        2. 9.4.1.2 Signal Clipping and Pulse Injector
        3. 9.4.1.3 DC Speaker Protection
        4. 9.4.1.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 9.4.1.5 Overtemperature Protection OTW and OTE
        6. 9.4.1.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 9.4.1.7 Fault Handling
        8. 9.4.1.8 Device Reset
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedures
          1. 10.2.1.2.1 Decoupling Capacitor Recommendations
          2. 10.2.1.2.2 PVDD Capacitor Recommendation
          3. 10.2.1.2.3 PCB Material Recommendation
          4. 10.2.1.2.4 Oscillator
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Typical Application, Single Ended (1N) SE
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Application Curves
      3. 10.2.3 Typical Application, Differential (2N), PBTL (Outputs Paralleled before LC filter)
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Application Curves
    3. 10.3 Typical Application, Differential (2N), PBTL (Outputs Paralleled after LC filter)
      1. 10.3.1 Design Requirements
      2. 10.3.2 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
      1. 11.1.1 VDD Supply
      2. 11.1.2 GVDD_X Supply
      3. 11.1.3 PVDD Supply
    2. 11.2 Powering Up
    3. 11.3 Powering Down
    4. 11.4 Thermal Design
      1. 11.4.1 Thermal Performance
      2. 11.4.2 Thermal Performance with Continuous Output Power
      3. 11.4.3 Thermal Performance with Non-Continuous Output Power
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
      1. 12.2.1 BTL Application Printed Circuit Board Layout Example
      2. 12.2.2 SE Application Printed Circuit Board Layout Example
      3. 12.2.3 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
      4. 12.2.4 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDW|44
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Differential Analog Inputs
  • Total Output Power at 10%THD+N
    • 60-W Stereo Continuous into 8 Ω in BTL Configuration at 30 V
    • 110-W Stereo Peak into 4 Ω in BTL Configuration at 30 V
  • Total Output Power at 1%THD+N
    • 50-W Stereo Continuous into 8 Ω in BTL Configuration at 30 V
    • 90-W Stereo Peak into 4 Ω in BTL Configuration at 30 V
  • Advanced Integrated Feedback Design with High-speed Gate Driver Error Correction
    (PurePath™ Ultra-HD)
    • Signal Bandwidth up to 100 kHz for High Frequency Content From HD Sources
    • Ultra Low 0.005% THD+N at 1 W into 4 Ω and <0.01% THD+N to Clipping
    • 60 dB PSRR (BTL, No Input Signal)
    • <55 µV (A-Weighted) Output Noise
    • >110 dB (A Weighted) SNR
  • Multiple Configurations Possible:
    • Stereo, Mono, 2.1 and 4xSE
  • Click and Pop Free Startup and Stop
  • 94% Efficient Class-D Operation (8 Ω)
  • Wide 12-V to 30-V Supply Voltage Operation
  • Self-Protection Design (Including Undervoltage, Overtemperature, Clipping, and Short Circuit Protection) With Error Reporting
  • EMI Compliant When Used With Recommended System Design

2 Applications

  • High End Soundbar
  • Mini Combo Systems
  • Blu-Ray Disc™ / DVD Receivers
  • Active Speakers

3 Description

The TPA3244 device is a high performance Class-D power amplifier that enables true premium sound quality with Class-D efficiency. It features an advanced integrated feedback design and proprietary high-speed gate driver error correction (PurePath™ Ultra-HD). This technology allows ultra low distortion across the audio band and superior audio quality. With a 30-V power supply the device can drive up to 2 x 110 W peak into 4-Ω load and 2 x 60 W continuous into 8-Ω load and features a 2-VRMS analog input interface that works seamlessly with high performance DACs such as Burr-Brown PCM52xx DAC Family from TI (that is, PCM5242 / PCM5252). In addition to excellent audio performance, TPA3244 achieves both high power efficiency and very low power stage idle losses below 0.45 W. This is achieved through the use of 65 mΩ MOSFETs and an optimized gate driver scheme that achieves significantly lower idle losses than typical discrete implementations.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPA3244 HTSSOP (44) 6.10mm x 14.00mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

TPA3244 FrontPageDiagram.gif

Total Harmonic Distortion

TPA3244 D000_SLASEC6.gif