SLASE93A August   2017  – November 2017 TLV320AIC3109-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Audio Data Serial Interface Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Hardware Reset
      2. 7.3.2  Digital Audio Data Serial Interface
        1. 7.3.2.1 Right-Justified Mode
        2. 7.3.2.2 Left-Justified Mode
        3. 7.3.2.3 I2S Mode
        4. 7.3.2.4 DSP Mode
        5. 7.3.2.5 TDM Data Transfer
      3. 7.3.3  Audio Data Converters
        1. 7.3.3.1 Audio Clock Generation
        2. 7.3.3.2 Mono Audio ADC
          1. 7.3.3.2.1 Mono Audio ADC High-Pass Filter
          2. 7.3.3.2.2 Automatic Gain Control (AGC)
            1. 7.3.3.2.2.1 Target Level
            2. 7.3.3.2.2.2 Attack Time
            3. 7.3.3.2.2.3 Decay Time
            4. 7.3.3.2.2.4 Noise Gate Threshold
            5. 7.3.3.2.2.5 Maximum PGA Gain Applicable
      4. 7.3.4  Mono Audio DAC
        1. 7.3.4.1 Digital Audio Processing for Playback
        2. 7.3.4.2 Digital Interpolation Filter
        3. 7.3.4.3 Delta-Sigma Audio DAC
        4. 7.3.4.4 Audio DAC Digital Volume Control
        5. 7.3.4.5 Increasing DAC Dynamic Range
        6. 7.3.4.6 Analog Output Common-mode Adjustment
      5. 7.3.5  Audio Analog Inputs
      6. 7.3.6  Analog Fully Differential Line Output Drivers
      7. 7.3.7  Analog High-Power Output Drivers
      8. 7.3.8  Output Stage Volume Controls
      9. 7.3.9  Input Impedance and VCM Control
      10. 7.3.10 MICBIAS Generation
      11. 7.3.11 Short-Circuit Output Protection
      12. 7.3.12 Jack and Headset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Path Mode
        1. 7.4.1.1 ADC PGA Signal Bypass Path Functionality
        2. 7.4.1.2 Passive Analog Bypass During Power Down
      2. 7.4.2 Digital Audio Processing for Record Path
    5. 7.5 Programming
      1. 7.5.1 I2C Control Interface
        1. 7.5.1.1 I2C Bus Debug in a Glitched System
    6. 7.6 Register Maps
      1. 7.6.1 Register Map Structure
      2. 7.6.2 Page 0 Registers
        1. 7.6.2.1  Register 0: Page Select (address = 0h) [reset = 0000 0000], Page 0
        2. 7.6.2.2  Register 1: Software Reset Register (address = 1h) [reset = 0000 0000], Page 0
        3. 7.6.2.3  Register 2: Codec Sample Rate Select Register (address = 2h) [reset = 0000 0000], Page 0
        4. 7.6.2.4  Register 3: PLL Programming Register A (address = 3h) [reset = 0001 0000], Page 0
        5. 7.6.2.5  Register 4: PLL Programming Register B (address = 4h) [reset = 0000 0100]
        6. 7.6.2.6  Register 5: PLL Programming Register C (address = 5h) [reset = 0000 0000], Page 0
        7. 7.6.2.7  Register 6: PLL Programming Register D (address = 6h) [reset = 0000 0000]
        8. 7.6.2.8  Register 7: Codec Data-Path Setup Register (address = 7h) [reset = 0000 0000], Page 0
        9. 7.6.2.9  Register 8: Audio Serial Data Interface Control Register A (address = 8h) [reset = 0000 0000], Page 0
        10. 7.6.2.10 Register 9: Audio Serial Data Interface Control Register B (address = 9h) [reset = 0000 0000], Page 0
        11. 7.6.2.11 Register 10: Audio Serial Data Interface Control Register C (address = Ah) [reset = 0000 0000], Page 0
        12. 7.6.2.12 Register 11: Audio Codec Overflow Flag Register (address = Bh) [reset = 0000 0001], Page 0
        13. 7.6.2.13 Register 12: Audio Codec Digital Filter Control Register (address = Ch) [reset = 0000 0000], Page 0
        14. 7.6.2.14 Register 13: Headset/Button Press Detection Register A (address = Dh) [reset = 0000 0000], Page 0
        15. 7.6.2.15 Register 14: Headset/Button Press Detection Register B (address = Eh) [reset = 0000 0000], Page 0
        16. 7.6.2.16 Register 15: ADC PGA Gain Control Register (address = Fh) [reset = 1000 0000], Page 0
        17. 7.6.2.17 Register 16: Auxiliary PGA Gain Control Register (address = Fh) [reset = 1000 0000], Page 0
        18. 7.6.2.18 Register 17-18: Reserved (address = 11h-12h) [reset = 1111 1111], Page 0
        19. 7.6.2.19 Register 19: MIC1P/LINE1P to ADC Control Register (address = 13h) [reset = 0111 1000], Page 0
        20. 7.6.2.20 Register 20: Reserved (address = 14h) [reset = 0111 1000], Page 0
        21. 7.6.2.21 Register 21: MIC2P/LINE2P to ADC Control Register (address = 15h) [reset = 0111 1000], Page 0
        22. 7.6.2.22 Registers 22-24: Reserved (address = 16h-18h) [reset = 0111 1000], Page 0
        23. 7.6.2.23 Register 25: MICBIAS Control Register (address = 25h) [reset = 0000 0110], Page 0
        24. 7.6.2.24 Register 26: AGC Control Register A (address = 1Ah) [reset = 0000 0000], Page 0
        25. 7.6.2.25 Register 27: AGC Control Register B (address = 1Bh) [reset = 1111 1110], Page 0
        26. 7.6.2.26 Register 28: AGC Control Register C (address = 1Ch) [reset = 0000 0000], Page 0
        27. 7.6.2.27 Register 29: Reserved (address = 1Dh) [reset = 0000 0000], Page 0
        28. 7.6.2.28 Register 30: Reserved (address = 1Eh) [reset = 1111 1110], Page 0
        29. 7.6.2.29 Register 31: Reserved (address = 1Fh) [reset = 0000 0000], Page 0
        30. 7.6.2.30 Register 32: AGC Gain Register (address = 20h) [reset = 1000 0000], Page 0
        31. 7.6.2.31 Register 33: Reserved (address = 21h) [reset = 0000 0000], Page 0
        32. 7.6.2.32 Register 34: AGC Noise Gate Debounce Register (address = 22h) [reset = 0000 0000], Page 0
        33. 7.6.2.33 Register 35: Reserved (address = 23h) [reset = 0000 0000], Page 0
        34. 7.6.2.34 Register 36: ADC Flag Register (address = 24h) [reset = 0000 0000], Page 0
        35. 7.6.2.35 Register 37: DAC Power and Output Driver Control Register (address = 25h) [reset = 0000 0000], Page 0
        36. 7.6.2.36 Register 38: High-Power Output Driver Control Register (address = 26h) [reset = 0000 0000], Page 0
        37. 7.6.2.37 Register 39: Reserved (address = 27h) [reset = 0000 0000], Page 0
        38. 7.6.2.38 Register 40: High-Power Output Stage Control Register (address = 28h) [reset = 0000 0000], Page 0
        39. 7.6.2.39 Register 41: DAC Output Switching Control Register (address = 29h) [reset = 0000 0000], Page 0
        40. 7.6.2.40 Register 42: Output Driver Pop Reduction Register (address = 2Ah) [reset = 0000 0000], Page 0
        41. 7.6.2.41 Register 43: DAC Digital Volume Control Register (address = 2Bh) [reset = 1000 0000], Page 0
        42. 7.6.2.42 Register 44: Reserved (address = 2Ch) [reset = 1000 0000], Page 0
        43. 7.6.2.43 Registers 45-50: Reserved (address = 2Dh-32h) [reset = 0000 0000], Page 0
        44. 7.6.2.44 Register 51: Reserved (address = 33h) [reset = 0000 0100], Page 0
        45. 7.6.2.45 Registers 52-57: Reserved (address = 34h-39h) [reset = 0000 0000], Page 0
        46. 7.6.2.46 Register 58: Reserved (address = 3Ah) [reset = 0000 0100], Page 0
        47. 7.6.2.47 Register 59: Reserved (address = 3Bh) [reset = 0000 0000], Page 0
        48. 7.6.2.48 Register 60: PGA to HPOUT Volume Control Register (address = 3Ch) [reset = 0000 0000], Page 0
        49. 7.6.2.49 Register 61: DAC_1 to HPOUT Volume Control Register (address = 3Dh) [reset = 0000 0000], Page 0
        50. 7.6.2.50 Register 62: Reserved Register (address = 3Eh) [reset = 0000 0000], Page 0
        51. 7.6.2.51 Register 63: PGA_AUX to HPOUT Volume Control Register (address = 3Fh) [reset = 0000 0000], Page 0
        52. 7.6.2.52 Register 64: Reserved (address = 40h) [reset = 0000 0000], Page 0
        53. 7.6.2.53 Register 65: HPOUT Output Level Control Register (address = 41h) [reset = 0000 0100], Page 0
        54. 7.6.2.54 Register 66: Reserved (address = 42h) [reset = 0000 0000], Page 0
        55. 7.6.2.55 Register 67: PGA to HPCOM Volume Control Register (address = 43h) [reset = 0000 0000], Page 0
        56. 7.6.2.56 Register 68: DAC_1 to HPCOM Volume Control Register (address = 44h) [reset = 0000 0000], Page 0
        57. 7.6.2.57 Register 69: Reserved (address = 45h) [reset = 0000 0000], Page 0
        58. 7.6.2.58 Register 70: PGA_AUX to HPCOM Volume Control Register (address = 46h) [reset = 0000 0000], Page 0
        59. 7.6.2.59 Register 71: Reserved (address = 47h) [reset = 0000 0000], Page 0
        60. 7.6.2.60 Register 72: HPCOM Output Level Control Register (address = 48h) [reset = 0000 0100], Page 0
        61. 7.6.2.61 Registers 73-80: Reserved (address = 49h-50h) [reset = 0000 0000], Page 0
        62. 7.6.2.62 Register 81: PGA to LEFT_LOP/M Volume Control Register (address = 51h) [reset = 0000 0000], Page 0
        63. 7.6.2.63 Register 82: DAC_1 to LEFT_LOP/M Volume Control Register (address = 52h) [reset = 0000 0000], Page 0
        64. 7.6.2.64 Register 83: Reserved (address = 53h) [reset = 0000 0000], Page 0
        65. 7.6.2.65 Register 84: PGA_AUX to LEFT_LOP/M Volume Control Register (address = 54h) [reset = 0000 0000], Page 0
        66. 7.6.2.66 Register 85: Reserved (address = 55h) [reset = 0000 0000], Page 0
        67. 7.6.2.67 Register 86: LEFT_LOP/M Output Level Control Register (address = 56h) [reset = 0000 0000], Page 0
        68. 7.6.2.68 Register 87: Reserved (address = 57h) [reset = 0000 0000], Page 0
        69. 7.6.2.69 Register 88: PGA to RIGHT_LOP/M Volume Control (address = 58h) [reset = 0000 0000], Page 0
        70. 7.6.2.70 Register 89: DAC_1 to RIGHT_LOP/M Volume Control (address = 59h) [reset = 0000 0000], Page 0
        71. 7.6.2.71 Register 90: Reserved (address = 5A) [reset = 0000 0000], Page 0
        72. 7.6.2.72 Register 91: PGA_AUX to RIGHT_LOP/M Volume Control (address = 5Bh) [reset = 0000 0000], Page 0
        73. 7.6.2.73 Register 92: Reserved (address = 5Ch) [reset = 0000 0000], Page 0
        74. 7.6.2.74 Register 93: RIGHT_LOP/M Output Level Control (address = 5Dh) [reset = 0000 0000], Page 0
        75. 7.6.2.75 Register 94: Module Power Status Register (address = 5Eh) [reset = 0000 0000], Page 0
        76. 7.6.2.76 Register 95: Output Driver Short-Circuit Detection Status Register (address = 5Fh) [reset = 0000 0000], Page 0
        77. 7.6.2.77 Register 96: Sticky Interrupt Flags Register (address = 60h) [reset = 0000 0000], Page 0
        78. 7.6.2.78 Register 97: Real-Time Interrupt Flags Register (address = 61h) [reset = 0000 0000], Page 0
        79. 7.6.2.79 Registers 98-100: Reserved (address = 62h-64h) [reset = 0000 0000], Page 0
        80. 7.6.2.80 Register 101: Clock Register (address = 65h) [reset = 0000 0000], Page 0
        81. 7.6.2.81 Register 102: Clock Generation Control Register (address = 66h) [reset = 0000 0000], Page 0
        82. 7.6.2.82 Register 103: AGC New Programmable Attack Time Register (address = 67h) [reset = 0000 0000], Page 0
        83. 7.6.2.83 Register 104: AGC New Programmable Decay Time Register (address = 68h) [reset = 0000 0000], Page 0
        84. 7.6.2.84 Registers 105-106: Reserved (address = 69h-6Ah) [reset = 0000 0000], Page 0
        85. 7.6.2.85 Register 107: New Programmable ADC Digital Path and I2C Bus Condition Register (address = 6Bh) [reset = 0000 0000], Page 0
        86. 7.6.2.86 Register 108: Passive Analog Signal Bypass Selection During Power Down Register (address = 6Ch) [reset = 0000 0000], Page 0
        87. 7.6.2.87 Register 109: DAC Quiescent Current Adjustment Register (address = 6Dh) [reset = 0000 0000], Page 0
        88. 7.6.2.88 Registers 110-127: Reserved (address = 6Eh-7Fh) [reset = 0000 0000], Page 0
      3. 7.6.3 Page 1 Register Descriptions
        1. 7.6.3.1  Register 0: Page Select Register (address = 0h) [reset = 0000 0000], Page 1
        2. 7.6.3.2  Register 1: Audio Effects Filter N0 Coefficient MSB Register (address = 1h) [reset = 0110 1011], Page 1
        3. 7.6.3.3  Register 2: Audio Effects Filter N0 Coefficient LSB Register (address = 2h) [reset = 1110 0011], Page 1
        4. 7.6.3.4  Register 3: Audio Effects Filter N1 Coefficient MSB Register (address = 3h) [reset = 1001 0110], Page 1
        5. 7.6.3.5  Register 4: Audio Effects Filter N1 Coefficient LSB Register (address = 4h) [reset = 0110 0110], Page 1
        6. 7.6.3.6  Register 5: Audio Effects Filter N2 Coefficient MSB Register (address = 5h) [reset = 0110 0111], Page 1
        7. 7.6.3.7  Register 6: Audio Effects Filter N2 Coefficient LSB Register (address = 6h) [reset = 0101 1101], Page 1
        8. 7.6.3.8  Register 7: Audio Effects Filter N3 Coefficient MSB Register (address = 7h) [reset = 0110 1011], Page 1
        9. 7.6.3.9  Register 8: Audio Effects Filter N3 Coefficient LSB Register (address = 8h) [reset = 1110 0011], Page 1
        10. 7.6.3.10 Register 9: Audio Effects Filter N4 Coefficient MSB Register (address = 9h) [reset = 1001 0110], Page 1
        11. 7.6.3.11 Register 10: Audio Effects Filter N4 Coefficient LSB Register (address = Ah) [reset = 0110 0110], Page 1
        12. 7.6.3.12 Register 11: Audio Effects Filter N5 Coefficient MSB Register (address = Bh) [reset = 0110 0111], Page 1
        13. 7.6.3.13 Register 12: Audio Effects Filter N5 Coefficient LSB Register (address = Ch) [reset = 0101 1101], Page 1
        14. 7.6.3.14 Register 13: Audio Effects Filter D1 Coefficient MSB Register (address = Dh) [reset = 0111 1101], Page 1
        15. 7.6.3.15 Register 14: Audio Effects Filter D1 Coefficient LSB Register (address = Eh) [reset = 1000 0011h], Page 1
        16. 7.6.3.16 Register 15: Audio Effects Filter D2 Coefficient MSB Register (address = Fh) [reset = 1000 0100], Page 1
        17. 7.6.3.17 Register 16: Audio Effects Filter D2 Coefficient LSB Register (address = 10h) [reset = 1110 1110], Page 1
        18. 7.6.3.18 Register 17: Audio Effects Filter D4 Coefficient MSB Register (address = 11h) [reset = 0111 1101], Page 1
        19. 7.6.3.19 Register 18: Audio Effects Filter D4 Coefficient LSB Register (address = 12h) [reset = 1000 0011], Page 1
        20. 7.6.3.20 Register 19: Audio Effects Filter D5 Coefficient MSB Register (address = 13h) [reset = 1000 0100], Page 1
        21. 7.6.3.21 Register 20: Audio Effects Filter D5 Coefficient LSB Register (address = 14h) [reset = 1110 1110], Page 1
        22. 7.6.3.22 Register 21: De-Emphasis Filter N0 Coefficient MSB Register (address = 15h) [reset = 0011 1001], Page 1
        23. 7.6.3.23 Register 22: De-Emphasis Filter N0 Coefficient LSB Register (address = 16h) [reset = 0101 0101], Page 1
        24. 7.6.3.24 Register 23: De-Emphasis Filter N1 Coefficient MSB Register (address = 17h) [reset = 1111 0011], Page 1
        25. 7.6.3.25 Register 24: De-Emphasis Filter N1 Coefficient LSB Register (address = 18h) [reset = 0010 1101], Page 1
        26. 7.6.3.26 Register 25: De-Emphasis Filter D1 Coefficient MSB Register (address = 19h) [reset = 0101 0011], Page 1
        27. 7.6.3.27 Register 26: De-Emphasis Filter D1 Coefficient LSB Register (address = 1Ah) [reset = 0111 1110], Page 1
        28. 7.6.3.28 Register 27: Reserved (address = 1Bh) [reset = 0110 1011], Page 1
        29. 7.6.3.29 Register 28: Reserved (address = 1Ch) [reset = 1110 0011], Page 1
        30. 7.6.3.30 Register 29: Reserved (address = 1Dh) [reset = 1001 0110], Page 1
        31. 7.6.3.31 Register 30: Reserved (address = 1Eh) [reset = 0110 0110], Page 1
        32. 7.6.3.32 Register 31: Reserved (address = 1Fh) [reset = 0110 0111], Page 1
        33. 7.6.3.33 Register 32: Reserved (address = 20h) [reset = 0101 1101], Page 1
        34. 7.6.3.34 Register 33: Reserved (address = 21h) [reset = 0110 1011], Page 1
        35. 7.6.3.35 Register 34: Reserved (address = 22h) [reset = 1110 0011], Page 1
        36. 7.6.3.36 Register 35: Reserved (address = 23h) [reset = 1001 0110], Page 1
        37. 7.6.3.37 Register 36: Reserved (address = 24h) [reset = 0110 0110], Page 1
        38. 7.6.3.38 Register 37: Reserved (address = 25h) [reset = 0110 0111], Page 1
        39. 7.6.3.39 Register 38: Reserved (address = 26h) [reset = 0101 1101], Page 1
        40. 7.6.3.40 Register 39: Reserved (address = 27h) [reset = 0111 1101], Page 1
        41. 7.6.3.41 Register 40: Reserved (address = 28h) [reset = 1000 0011], Page 1
        42. 7.6.3.42 Register 41: Reserved (address = 29h) [reset = 1000 0100], Page 1
        43. 7.6.3.43 Register 42: Reserved (address = 2Ah) [reset = 1110 1110], Page 1
        44. 7.6.3.44 Register 43: Reserved (address = 2Bh) [reset = 0111 1101], Page 1
        45. 7.6.3.45 Register 44: Reserved (address = 2Ch) [reset = 1000 0011], Page 1
        46. 7.6.3.46 Register 45: Reserved (address = 2Dh) [reset = 1000 0100], Page 1
        47. 7.6.3.47 Register 46: Reserved (address = 2Eh) [reset = 1110 1110], Page 1
        48. 7.6.3.48 Register 47: Reserved (address = 2Fh) [reset = 0011 1001], Page 1
        49. 7.6.3.49 Register 48: Reserved (address = 30h) [reset = 0101 0101], Page 1
        50. 7.6.3.50 Register 49: Reserved (address = 31h) [reset = 1111 0011], Page 1
        51. 7.6.3.51 Register 50: Reserved (address = 32h) [reset = 0010 1101], Page 1
        52. 7.6.3.52 Register 51: Reserved (address = 33h) [reset = 0101 0011], Page 1
        53. 7.6.3.53 Register 52: Reserved (address = 34h) [reset = 0111 1110], Page 1
        54. 7.6.3.54 Register 53: Reserved (address = 35h) [reset = 0111 1111], Page 1
        55. 7.6.3.55 Register 54: Reserved (address = 36h) [reset = 1111 1111], Page 1
        56. 7.6.3.56 Registers 55-64: Reserved (address = 37h-40h) [reset = 0000 0000], Page 1
        57. 7.6.3.57 Register 65: ADC High-Pass Filter N0 Coefficient MSB Register (address = 41h) [reset = 0011 1001], Page 1
        58. 7.6.3.58 Register 66: ADC High-Pass Filter N0 Coefficient LSB Register (address = 42h) [reset = 1110 1010], Page 1
        59. 7.6.3.59 Register 67: Channel ADC High-Pass Filter N1 Coefficient MSB Register (address = 43h) [reset = 1000 0000 , Page 1
        60. 7.6.3.60 Register 68: Channel ADC High-Pass Filter N1 Coefficient LSB Register (address = 44h) [reset = 0001 0110], Page 1
        61. 7.6.3.61 Register 69: Channel ADC High-Pass Filter D1 Coefficient MSB Register (address = 45h) [reset = 0111 1111], Page 1
        62. 7.6.3.62 Register 70: Channel ADC High-Pass Filter D1 Coefficient LSB Register (address = 46h) [reset = 1101 0101], Page 1
        63. 7.6.3.63 Register 71: Reserved (address = 47h) [reset = 0111 1111], Page 1
        64. 7.6.3.64 Register 72: Reserved (address = 48h) [reset = 1110 1010], Page 1
        65. 7.6.3.65 Register 73: Reserved (address = 49h) [reset = 1000 0000], Page 1
        66. 7.6.3.66 Register 74: Reserved (address = 4Ah) [reset = 0001 0110], Page 1
        67. 7.6.3.67 Register 75: Reserved (address = 4Bh) [reset = 0111 1111], Page 1
        68. 7.6.3.68 Register 76: Reserved (address = 4Ch) [reset = 1101 0101], Page 1
        69. 7.6.3.69 Registers 77h-127h: Reserved (address = 4Dh) [reset = 0000 0000], Page 1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Temperature Grade 2: –40°C to +105°C
    • HBM ESD Classification 2
    • CDM ESD Classification C4B
  • Mono Audio DAC:
    • 102-dBA Signal-to-Noise Ratio
    • Supports Sample Rates From 8 kHz to 96 kHz
    • 3D, Bass, Treble, EQ, or De-Emphasis Effects
  • Mono Audio ADC:
    • 92-dBA Signal-to-Noise Ratio
    • Supports Sample Rates From 8 kHz to 96 kHz
    • Digital Signal Processing and Noise Filtering
  • Four Audio Input Pins:
    • Up to Two Differential Inputs
    • Up to Two Single-Ended Inputs
  • Six Audio Output Drivers:
    • One Fully Differential or Two Single-Ended Headphone Drivers
    • Mono Pair of Fully-Differential Line Outputs
  • Low Power: 14-mW Mono, 48-kHz Playback With 3.3-V Analog Supply
  • Ultra-Low Power Mode With Passive Analog Bypass
  • Front-End Programmable Gain Amplifier (PGA)
  • Programmable Digital Gain for DAC Playback
  • Automatic Gain Control (AGC) for Record
  • Programmable Microphone Bias
  • Programmable PLL for Flexible Clock Generation
  • I2C Control Bus
  • Audio Data Formats: I2S, Left- and Right-Justified, DSP, and TDM
  • Power Supplies:
    • Analog (AVDD, DRVDD): 2.7 V to 3.6 V
    • Digital Core (DVDD): 1.525 V to 1.95 V
    • Digital I/O (IOVDD): 1.1 V to 3.6 V
  • Available in Two VQFN-32 Package Options:
    • Non-Wettable (6PAIC3109TRHBRQ1)
    • Wettable-Flank (6PAIC3109TWRHMRQ1)

2 Applications

  • Emergency Call (eCall) Systems
  • Telematics Control Unit (TCU)
  • Automotive Head Units

3 Description

The TLV320AIC3109-Q1 device is a low-power mono audio codec with a mono headphone amplifier and multiple input and output channels that are programmable in single-ended or fully differential configurations. The device includes extensive register-based power control, allowing 48-kHz digital-to-analog converter (DAC) playback at as little as
14-mW consumption, making the device well-suited for low-power applications.

The record path of the TLV320AIC3109-Q1 contains integrated microphone bias, a digitally controlled microphone preamplifier, automatic gain control (AGC), a flexible front-end multiplexer (MUX), and a front-end analog mixer (MIX). During record, programmable filters can remove audible noise. The playback path includes MIX and MUX capability from the mono DAC and selected inputs, through programmable volume controls, to the various outputs.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TLV320AIC3109-Q1 VQFN (32) 5.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

SPACE

Simplified Diagram

TLV320AIC3109-Q1 FP_circuit_slase93.gif

4 Revision History

Changes from * Revision (August 2017) to A Revision

  • Released 6PAIC3109TWRHMRQ1 (wettable-flank package option) to productionGo
  • Added TI Design to documentGo