SLAS548D October   2008  – September 2015 TLV320ADC3001

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Dissipation Ratings
    7. 8.7  I2S/LJF/RJF Timing in Master Mode
    8. 8.8  DSP Timing in Master Mode
    9. 8.9  I2S/LJF/RJF Timing in Slave Mode
    10. 8.10 DSP Timing in Slave Mode
    11. 8.11 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  PLL Start-up
      3. 10.3.3  Software Power Down
      4. 10.3.4  miniDSP
      5. 10.3.5  Audio Data Converters
      6. 10.3.6  Digital Audio Data Serial Interface
        1. 10.3.6.1 Right-Justified Mode
        2. 10.3.6.2 Left-Justified Mode
        3. 10.3.6.3 I2S Mode
        4. 10.3.6.4 DSP Mode
      7. 10.3.7  Audio Clock Generation
      8. 10.3.8  Stereo Audio ADC
      9. 10.3.9  Audio Analog Inputs
        1. 10.3.9.1 Digital Volume Control
        2. 10.3.9.2 Fine Digital Gain Adjustment
        3. 10.3.9.3 AGC
      10. 10.3.10 Input Impedance and VCM Control
      11. 10.3.11 MICBIAS Generation
      12. 10.3.12 ADC Decimation Filtering and Signal Processing
        1. 10.3.12.1 Processing Blocks
        2. 10.3.12.2 Processing Blocks - Details
          1. 10.3.12.2.1 First-Order IIR, AGC, Filter A
          2. 10.3.12.2.2 Five Biquads, First-Order IIR, AGC, Filter A
          3. 10.3.12.2.3 25-Tap FIR, First-Order IIR, AGC, Filter A
          4. 10.3.12.2.4 First-Order IIR, AGC, Filter B
          5. 10.3.12.2.5 Three Biquads, First-Order IIR, AGC, Filter B
          6. 10.3.12.2.6 20-Tap FIR, First-Order IIR, AGC, Filter B
          7. 10.3.12.2.7 First-Order IIR, AGC, Filter C
          8. 10.3.12.2.8 Five Biquads, First-Order IIR, AGC, Filter C
          9. 10.3.12.2.9 25-Tap FIR, First-Order IIR, AGC, Filter C
        3. 10.3.12.3 User-Programmable Filters
          1. 10.3.12.3.1 First-Order IIR Section
          2. 10.3.12.3.2 Biquad Section
          3. 10.3.12.3.3 FIR Section
        4. 10.3.12.4 Decimation Filter
          1. 10.3.12.4.1 Decimation Filter A
          2. 10.3.12.4.2 Decimation Filter B
          3. 10.3.12.4.3 Decimation Filter C
    4. 10.4 Device Functional Modes
      1. 10.4.1 Recording Mode
    5. 10.5 Programming
      1. 10.5.1 Digital Interfaces
        1. 10.5.1.1 I2C Control Mode
    6. 10.6 Register Maps
      1. 10.6.1 Control Registers
      2. 10.6.2 Control Registers, Page 0: Clock Multipliers and Dividers, Serial Interfaces, Flags, Interrupts and Programming of GPIOs
      3. 10.6.3 CONTROL REGISTERS Page 1: ADC Routing, PGA, Power-Controls, Etc.
      4. 10.6.4 Control Registers, Page 4: ADC Digital Filter Coefficients
      5. 10.6.5 Control Registers, Page 5: ADC Programmable Coefficients RAM (65:127)
      6. 10.6.6 Control Registers, Page 32: ADC DSP Engine Instruction RAM (0:31)
        1. 10.6.6.1 Page 32 / Register 5 Through Page 32 / Register 97
      7. 10.6.7 Control Registers, Page 33 Through Page 47: ADC DSP Engine Instruction RAM (32:63) Through (480:511)
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 ADC Setup
          1. 11.2.2.1.1 Step 1
          2. 11.2.2.1.2 Step 2
          3. 11.2.2.1.3 Example Register Setup to Record Analog Data Through ADC to Digital Out
        2. 11.2.2.2 MICBIAS
        3. 11.2.2.3 Decoupling Capacitors
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Community Resources
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
    4. 14.4 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Stereo Audio ADC
    • 92-dBA Signal-to-Noise Ratio
    • Supports ADC Sample Rates From 8 kHz to 96 kHz
  • Instruction-Programmable Embedded miniDSP
  • Flexible Digital Filtering With RAM Programmable Coefficient, Instructions, and Built-In Standard Modes
    • Low-Latency IIR Filters for Voice
    • Linear Phase FIR Filters for Audio
    • Additional Programmable IIR Filters for EQ, Noise Cancellation, or Reduction
    • Up to 128 Programmable ADC Digital Filter Coefficients
  • Three Audio Inputs With Configurable Automatic Gain Control (AGC)
    • Programmable in Single-Ended or Fully Differential Configurations
    • Can Be Driven Hi-Z for Easy Interoperability With Other Audio ICs
  • Low Power Consumption and Extensive Modular Power Control:
    • 6-mW Mono Record 8-kHz
    • 11-mW Stereo Record, 8-kHz
    • 10-mW Mono Record, 48-kHz
    • 17-mW Stereo Record, 48-kHz
  • Programmable Microphone Bias
  • Programmable PLL for Clock Generation
  • I2C Control Bus
  • Audio Serial Data Bus Supports I2S, Left/Right-Justified, DSP, PCM, and TDM Modes
  • Power Supplies:
    • Analog: 2.6 V–3.6 V.
    • Digital: Core: 1.65 V–1.95 V,
      I/O: 1.1 V–3.6 V
  • 2.24-mm × 2.16-mm NanoFree™ 16-Ball 16-YZH Wafer Chip Scale Package (WCSP)

2 Applications

  • Wireless Handsets
  • Portable Low-Power Audio Systems
  • Noise Cancellation Systems
  • Front-End Voice or Audio Processor for Digital Audio

3 Description

The TLV320ADC3001 device is a low-power, stereo audio analog-to-digital converter (ADC) supporting sampling rates from 8 kHz to 96 kHz with an integrated programmable-gain amplifier providing up to 40-dB analog gain or AGC. A programmable miniDSP is provided for custom audio processing. Front-end input coarse attenuation of 0 dB, –6 dB, or off, is also provided. The inputs are programmable in a combination of single-ended or fully differential configurations. Extensive register-based power control is available via I2C, enabling mono or stereo recording. Low power consumption makes the TLV320ADC3001 ideal for battery-powered portable equipment.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TLV320ADC3001 DSBGA (16) 2.24 mm × 2.16 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

TLV320ADC3001 ADC3001_Key.gif