SLASF37A
January 2024 – January 2025
TAA5412-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements: I2C Interface
5.7
Switching Characteristics: I2C Interface
5.8
Timing Requirements: SPI Interface
5.9
Switching Characteristics: SPI Interface
5.10
Timing Requirements: TDM, I2S or LJ Interface
5.11
Switching Characteristics: TDM, I2S or LJ Interface
5.12
Timing Requirements: PDM Digital Microphone Interface
5.13
Switching Characteristics: PDM Digial Microphone Interface
5.14
Timing Diagrams
5.15
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Serial Interfaces
6.3.1.1
Control Serial Interfaces
6.3.1.2
Audio Serial Interfaces
6.3.1.2.1
Time Division Multiplexed Audio (TDM) Interface
6.3.1.2.2
Inter IC Sound (I2S) Interface
6.3.1.2.3
Left-Justified (LJ) Interface
6.3.1.3
Using Multiple Devices With Shared Buses
6.3.2
Phase-Locked Loop (PLL) and Clock Generation
6.3.3
Input Channel Configuration
6.3.4
Reference Voltage
6.3.5
Microphone Bias
6.3.6
Digital PDM Microphone Record Channel
6.3.7
Signal-Chain Processing
6.3.7.1
ADC Signal-Chain
6.3.7.1.1
6 to 4 Input Select Multiplexer (6:4 MUX)
6.3.7.1.2
Programmable Channel Gain and Digital Volume Control
6.3.7.1.3
Programmable Channel Gain Calibration
6.3.7.1.4
Programmable Channel Phase Calibration
6.3.7.1.5
Programmable Digital High-Pass Filter
6.3.7.1.6
Programmable Digital Biquad Filters
6.3.7.1.7
Programmable Channel Summer and Digital Mixer
6.3.7.1.8
Configurable Digital Decimation Filters
6.3.7.1.8.1
Linear-phase filters
6.3.7.1.8.1.1
Sampling Rate: 8kHz or 7.35kHz
6.3.7.1.8.1.2
Sampling Rate: 16kHz or 14.7kHz
6.3.7.1.8.1.3
Sampling Rate: 24kHz or 22.05kHz
6.3.7.1.8.1.4
Sampling Rate: 32kHz or 29.4kHz
6.3.7.1.8.1.5
Sampling Rate: 48kHz or 44.1kHz
6.3.7.1.8.1.6
Sampling Rate: 96kHz or 88.2kHz
6.3.7.1.8.1.7
Sampling Rate: 192kHz or 176.4kHz
6.3.7.1.8.1.8
Sampling Rate: 384kHz or 352.8kHz
6.3.7.1.8.1.9
Sampling Rate: 768kHz or 705.6kHz
6.3.7.1.8.2
Low-latency Filters
6.3.7.1.8.2.1
Sampling Rate: 24kHz or 22.05kHz
6.3.7.1.8.2.2
Sampling Rate: 32kHz or 29.4kHz
6.3.7.1.8.2.3
Sampling Rate: 48kHz or 44.1kHz
6.3.7.1.8.2.4
Sampling Rate: 96kHz or 88.2kHz
6.3.7.1.8.2.5
Sampling Rate: 192kHz or 176.4kHz
6.3.7.1.8.3
Ultra-Low-Latency Filters
6.3.7.1.8.3.1
Sampling Rate: 24kHz or 22.05kHz
6.3.7.1.8.3.2
Sampling Rate: 32kHz or 29.4kHz
6.3.7.1.8.3.3
Sampling Rate: 48kHz or 44.1kHz
6.3.7.1.8.3.4
Sampling Rate: 96kHz or 88.2kHz
6.3.7.1.8.3.5
Sampling Rate: 192kHz or 176.4kHz
6.3.7.1.9
Automatic Gain Controller (AGC)
6.3.7.1.10
Voice Activity Detection (VAD)
6.3.7.1.11
Ultrasonic Activity Detection (UAD)
6.3.8
Interrupts, Status, and Digital I/O Pin Multiplexing
6.3.9
Input DC Fault Diagnostics
6.3.10
Power Tune Mode
6.4
Device Functional Modes
6.4.1
Sleep Mode or Software Shutdown
6.4.2
Software Reset
6.4.3
Active Mode
6.5
Programming
6.5.1
Control Serial Interfaces
6.5.1.1
I2C Control Interface
6.5.1.1.1
General I2C Operation
6.5.1.1.2
I2C Single-Byte and Multiple-Byte Transfers
6.5.1.1.2.1
I2C Single-Byte Write
6.5.1.1.2.2
I2C Multiple-Byte Write
6.5.1.1.2.3
I2C Single-Byte Read
6.5.1.1.2.4
I2C Multiple-Byte Read
6.5.1.2
SPI Control Interface
7
Register Maps
7.1
Device Configuration Registers
7.1.1
TAA5412-Q1_B0_P0 Registers
7.1.2
TAA5412-Q1_B0_P1 Registers
7.1.3
TAA5412-Q1_B0_P3 Registers
7.2
Programmable Coefficient Registers
7.2.1
Programmable Coefficient Registers: Page 8
7.2.2
Programmable Coefficient Registers: Page 9
7.2.3
Programmable Coefficient Registers: Page 10
7.2.4
Programmable Coefficient Registers: Page 11
7.2.5
Programmable Coefficient Registers: Page 19
7.2.6
Programmable Coefficient Registers: Page 27
7.2.7
Programmable Coefficient Registers: Page 28
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Application
8.2.2
Design Requirements
8.2.3
Detailed Design Procedure
8.2.4
Application Performance Plots
8.2.5
Example Device Register Configuration Scripts for EVM Setup
8.3
Power Supply Recommendations
8.3.1
IOVDD_IO_MODE for 1.8V and 1.2V Operation
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Revision History
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTV|32
MPQF166B
RGE|24
MPQF124G
Thermal pad, mechanical data (Package|Pins)
Data Sheet
TAA5412-Q1 Automotive stereo audio ADC with 112dB dynamic range, high-voltage input, micbias and diagnostics