SCES416N December   2002  – January 2017 SN74LVC1G97

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Max tpd of 6.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Choose From Nine Specific Logic Functions

2 Applications

  • Barcode Scanners
  • Cable Solutions
  • E-Books
  • Embedded PCs
  • Field Transmitter: Temperature or Pressure Sensors
  • Fingerprint Biometrics
  • HVAC: Heating, Ventilating, and Air Conditioning
  • Network-Attached Storage (NAS)
  • Server Motherboards and PSUs
  • Software Defined Radios (SDR)
  • TVs: High Definition (HDTV), LCD, and Digital
  • Video Communications Systems
  • Wireless Data Access Cards, Headsets, Keyboard, Mouse, and LAN Cards

3 Description

The SN74LVC1G97 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputs can be connected to VCC or GND.

This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.

This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

NanoFree package technology is a major break-through in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC1G97DBV SOT-23 (6) 2.90 mm × 1.60 mm
SN74LVC1G97DCK SC70 (6) 2.00 mm × 1.25 mm
SN74LVC1G97DRL SOT (6) 1.60 mm × 1.20 mm
SN74LVC1G97DRY 1.45 mm × 1.00 mm
SN74LVC1G97DSF 1.00 mm × 1.00 mm
SN74LVC1G97YZP DSBGA (6) 1.41 mm × 0.91 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN74LVC1G97 ld_ces416.gif