SLLSFI8 February   2021 SN55LVCP22A-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Select Pins
      2. 8.3.2 Output Enable Pins
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Current-Mode Logic (CML)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Single-Ended (LVPECL)
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
      4. 9.2.4 Low-Voltage Differential Signaling (LVDS)
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
      5. 9.2.5 Cold Sparing
      6. 9.2.6 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • QML class V, RHA, SMD 5962-11242
  • Radiation performance
    • RHA to 100 krad(Si)
    • ELDRS free to 100 krad(Si)
    • SEL immune to LET = 75 MeV⋅cm2/mg
    • SEE characterized to LET = 75 MeV⋅cm2/mg
  • High-speed (up to 1000 Mbps)
  • Low-jitter fully differential data path
  • 50 ps (typ), of peak-to-peak jitter with
    PRBS = 223–1 pattern
  • Less than 227 mW (typ), 313 mW (max) total power dissipation
  • Output (channel-to-channel) skew is 80 ps (typ)
  • Configurable as 2:1 mux, 1:2 demux, repeater or 1:2 signal splitter
  • Inputs accept LVDS, LVPECL, and CML signals
  • Fast switch time of 1.7 ns (typ)
  • Fast propagation delay of 0.65 ns (typ)
  • Inter-operates with TIA/EIA-644-A LVDS standard
  • Supports defense, aerospace, and medical applications:
    • Controlled baseline
    • One assembly/test site and one fabrication site
    • Extended product life cycle and extended product-change notification
    • Product traceability