SNVSAA6A February   2015  – March 2015 LMR14050

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency Peak Current Mode Control
      2. 8.3.2  Slope Compensation
      3. 8.3.3  Sleep-mode
      4. 8.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 8.3.5  Adjustable Output Voltage
      6. 8.3.6  Enable and Adjustable Under-voltage Lockout
      7. 8.3.7  External Soft-start
      8. 8.3.8  Switching Frequency and Synchronization (RT/SYNC)
      9. 8.3.9  Over Current and Short Circuit Protection
      10. 8.3.10 Overvoltage Protection
      11. 8.3.11 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Set-Point
        2. 9.2.2.2 Switching Frequency
        3. 9.2.2.3 Output Inductor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Schottky Diode Selection
        6. 9.2.2.6 Input Capacitor Selection
        7. 9.2.2.7 Bootstrap Capacitor Selection
        8. 9.2.2.8 Soft-start Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 4 V to 40 V Input Range
  • 5 A Continuous Output Current
  • Ultra-low 40 µA Operating Quiescent Current
  • 90 mΩ High-Side MOSFET
  • Minimum Switch-On Time: 75 ns
  • Current Mode Control
  • Adjustable Switching Frequency from 200 kHz to 2.5 MHz
  • Frequency Synchronization to External Clock
  • Internal Compensation for Ease of Use
  • High Duty Cycle Operation Supported
  • Precision Enable Input
  • 1 µA Shutdown Current
  • External Soft-start
  • Thermal, Overvoltage and Short Protection
  • 8-Pin HSOIC with PowerPAD™ Package

2 Applications

  • Automotive Battery Regulation
  • Industrial Power Supplies
  • Telecom and Datacom Systems
  • Battery Powered System

3 Description

The LMR14050 is a 40 V, 5 A step down regulator with an integrated high-side MOSFET. With a wide input range from 4 V to 40 V, it’s suitable for various applications from industrial to automotive for power conditioning from unregulated sources. The regulator’s quiescent current is 40 µA in Sleep-mode, which is suitable for battery powered systems. An ultra-low 1 μA current in shutdown mode can further prolong battery life. A wide adjustable switching frequency range allows either efficiency or external component size to be optimized. Internal loop compensation means that the user is free from the tedious task of loop compensation design. This also minimizes the external components of the device. A precision enable input allows simplification of regulator control and system power sequencing. The device also has built-in protection features such as cycle-by-cycle current limit, thermal sensing and shutdown due to excessive power dissipation, and output overvoltage protection.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMR14050SDDA HSOIC-8 4.89 mm x 3.90 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematic

LMR14050 simplified_sch_snvsa81.gif

Efficiency vs Output Current

LMR14050 D001_eff_vs_curr_SNVSA81.gif