SPRAD57 August   2022 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Jacinto™ 7 Safety Architecture Concepts
    1. 1.1 Safety Architectural Overview: MCU Island and Extended MCU Island
    2. 1.2 Implementing Mixed Criticality - Freedom from Interference (FFI)
  4. 2Overview of Safety Mechanisms
  5. 3Implementation of Safety in Your System
    1. 3.1 Hardware Collateral
    2. 3.2 Software Support

Abstract

In this document, we will introduce Jacinto 7 safety fundamentals and the collateral TI provides for customers' functional safety implementation.

Jacinto SoCs are developed as a functional Safety Element Out of Context (SEooC) via ISO26262/IEC61508 processes to achieve ASIL-D/SIL-3 systematic fault integrity and includes hardware diagnostics to achieve up ASIL-D/SIL-3 random fault integrity. The device has gone through safety assessment by a certified third party (TUV-SUD) and a certificate will be provided.

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