SPRACU5D June   2021  – January 2025 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Application Note Usage Guidelines
      1. 1.1.1 Custom Board Design - Implementation References
      2. 1.1.2 Processor Family Specific Application Note
      3. 1.1.3 Schematics Design Guidelines
      4. 1.1.4 Schematic Review Checklist
      5. 1.1.5 FAQ Reference for Application Note Usage Guidelines
    2. 1.2 Family Wise List of Processors
      1. 1.2.1 AM64x Family of Processors
      2. 1.2.2 AM243x Family of Processors
  5. 2 Related Collateral
    1. 2.1 Links to Commonly Available and Applicable Collaterals
    2. 2.2 Hardware Design Considerations for Custom Board Design
  6. 3 Processor Selection
    1. 3.1 Data Sheet Use Case and Version Referenced
    2. 3.2 Processor Selection (OPN Orderable Part Number)
    3. 3.3 Peripheral Instance Naming Convention
    4. 3.4 Unused Peripherals
    5. 3.5 Processor Ordering and Quality
    6. 3.6 Processor Selection Checklist
  7. 4 Power Architecture
    1. 4.1 Generating Supply Rails
      1. 4.1.1 Power Management IC (PMIC)
        1. 4.1.1.1 PMIC Checklist
        2. 4.1.1.2 Additional References
      2. 4.1.2 Discrete Power
        1. 4.1.2.1 DC/DC Converter
        2. 4.1.2.2 LDO
        3. 4.1.2.3 Discrete Power Checklist
    2. 4.2 Power Control and Circuit Protection
      1. 4.2.1 Load Switch (Power Switching)
        1. 4.2.1.1 Load Switch Checklist
      2. 4.2.2 eFuse IC (Power Switching and Protection)
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (EVM) or Starter Kit (SK)
      1. 5.1.1 Evaluation Module Checklist
    2. 5.2 Processor-Specific EVM or SK Versus Data Sheet
      1. 5.2.1 Notes About Component Selection
        1. 5.2.1.1 Series Resistor
        2. 5.2.1.2 Parallel Pull Resistor
        3. 5.2.1.3 Drive Strength Configuration
        4. 5.2.1.4 Data Sheet Recommendations
        5. 5.2.1.5 Processor IOs - External ESD Protection
        6. 5.2.1.6 Peripheral Clock Output Series Resistors
        7. 5.2.1.7 Component Selection Checklist
      2. 5.2.2 Additional Information Regarding Reuse of EVM or SK Design
        1. 5.2.2.1 Updated EVM or SK Schematic With Design, Review and CAD Notes Added
        2. 5.2.2.2 EVM or SK Design Files Reuse
          1. 5.2.2.2.1 Reuse of EVM or SK Design Checklist
    3. 5.3 Before Beginning the Design
      1. 5.3.1  Documentation
      2. 5.3.2  Processor Pin Attributes (Pinout) Verification
      3. 5.3.3  Device Comparison, IOSET and Voltage Conflict
      4. 5.3.4  RSVD Reserved Pins (Signals)
      5. 5.3.5  Note on PADCONFIG Register
      6. 5.3.6  Processor IO (Signal) Isolation for Fail-Safe Operation
      7. 5.3.7  References to Processor-Specific EVM or SK
      8. 5.3.8  High-Speed Interface Design Guidelines
      9. 5.3.9  Recommended Current Source or Sink for LVCMOS (GPIO) Outputs
      10. 5.3.10 Connection of Slow Ramp Inputs or Capacitors to LVCMOS IOs (Inputs or Outputs)
      11. 5.3.11 Queries and Clarifications Related to Processor During Custom Board Design
      12. 5.3.12 Before Beginning the Design Checklist
      13. 5.3.13 Device Recommendations
  9. 6 Processor Recommendations
    1. 6.1 Common (Processor Start-Up) Connection
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Supplies for Core and Peripherals
          1. 6.1.1.1.1 Power Supply Ramp (Slew Rate) Requirements and Dynamic Voltage Scaling / Change
          2. 6.1.1.1.2 Processor Core and Peripheral Core Power Supply Checklist
          3. 6.1.1.1.3 Peripheral Analog Power Supply Checklist
        2. 6.1.1.2 Supply for IO Groups
          1. 6.1.1.2.1 Supply for IO Groups Checklist
        3. 6.1.1.3 Supply for VPP (eFuse ROM Programming)
          1. 6.1.1.3.1 VPP Checklist
        4. 6.1.1.4 Additional Information
      2. 6.1.2 Capacitors for Supply Rails
        1. 6.1.2.1 Additional Information
        2. 6.1.2.2 Capacitors for Supply Rails Checklist
      3. 6.1.3 Processor Clock
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 High Frequency Oscillator (MCU_OSC0_XI/ MCU_OSC0_XO)
          2. 6.1.3.1.2 EXT_REFCLK1 (External Clock Input to Main Domain)
          3. 6.1.3.1.3 Additional Information
          4. 6.1.3.1.4 Clock Input Checklist - MCU_OSC0
        2. 6.1.3.2 Clock Output
          1. 6.1.3.2.1 Clock Output Checklist
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 External Reset Inputs
        2. 6.1.4.2 Reset Status Outputs
        3. 6.1.4.3 Additional Information
        4. 6.1.4.4 Processor Reset Input Checklist
        5. 6.1.4.5 Processor Reset Status Output Checklist
      5. 6.1.5 Configuration of Boot Modes for Processors
        1. 6.1.5.1 Processor Boot Mode Inputs Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Boot Mode Selection
          1. 6.1.5.2.1 Notes on USB Boot Mode
        3. 6.1.5.3 Boot Mode Implementation Approaches
        4. 6.1.5.4 Additional Information
        5. 6.1.5.5 Configuration of Boot Modes (for Processor) Checklist
    2. 6.2 Board Debug Using JTAG and EMU
      1. 6.2.1 JTAG and EMU Used
      2. 6.2.2 JTAG and EMU Not Used
      3. 6.2.3 Additional Information
      4. 6.2.4 Board Debug Using JTAG and EMU Checklist
  10. 7 Processor Peripherals
    1. 7.1 Power Supply Connections for IO Groups
      1. 7.1.1 Supply Connections for IO Groups Checklist
    2. 7.2 Memory Interface (DDRSS (DDR4/LPDDR4), MMCSD (eMMC/SD/SDIO), OSPI/QSPI and GPMC)
      1. 7.2.1 DDR Subsystem (DDRSS)
        1. 7.2.1.1 DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.1.1 Memory Interface Configuration
          2. 7.2.1.1.2 Routing Topology and Terminations
          3. 7.2.1.1.3 Resistors for Control and Calibration
          4. 7.2.1.1.4 Capacitors for the Power Supply Rails
          5. 7.2.1.1.5 Data Bit or Byte Swapping
          6. 7.2.1.1.6 VTT Termination Schematics Reference
          7. 7.2.1.1.7 DDR4 Implementation Checklist
        2. 7.2.1.2 LPDDR4 SDRAM (Low-Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.2.1 Memory Interface Configuration
          2. 7.2.1.2.2 Routing Topology and Terminations
          3. 7.2.1.2.3 Resistors for Control and Calibration
          4. 7.2.1.2.4 Capacitors for the Power Supply Rails
          5. 7.2.1.2.5 Data Bit or Byte Swapping
          6. 7.2.1.2.6 LPDDR4 Implementation Checklist
      2. 7.2.2 Multi-Media Card and Secure Digital (MMCSD)
        1. 7.2.2.1 MMC0 - eMMC (Embedded Multimedia Card) Interface
          1. 7.2.2.1.1 MMC0 Used
            1. 7.2.2.1.1.1 IO Power Supply
            2. 7.2.2.1.1.2 eMMC (Attached Device) Reset
            3. 7.2.2.1.1.3 Signals Connection
            4. 7.2.2.1.1.4 Capacitors for the Power Supply Rails
          2. 7.2.2.1.2 MMC0 Not Used
          3. 7.2.2.1.3 MMC0 (eMMC) Checklist
          4. 7.2.2.1.4 Additional Information on eMMC PHY
          5. 7.2.2.1.5 MMC0 SD (Secure Digital) Card Interface
        2. 7.2.2.2 MMC1 – SD (Secure Digital) Card Interface
          1. 7.2.2.2.1 IO Power Supply
          2. 7.2.2.2.2 SD Card Supply Reset and Boot Configuration
          3. 7.2.2.2.3 Signals Connection
          4. 7.2.2.2.4 ESD Protection
          5. 7.2.2.2.5 Capacitors for the Power Supply Rails
          6. 7.2.2.2.6 MMC1 SD Card Interface Checklist
        3. 7.2.2.3 Additional Information
      3. 7.2.3 Octal Serial Peripheral Interface (OSPI) or Quad Serial Peripheral Interface (QSPI)
        1. 7.2.3.1 IO Power Supply
        2. 7.2.3.2 OSPI or QSPI Device Reset
        3. 7.2.3.3 Signals Connection
        4. 7.2.3.4 Loopback Clock
        5. 7.2.3.5 Interface to Multiple Devices
        6. 7.2.3.6 Capacitors for the Power Supply Rails
        7. 7.2.3.7 OSPI or QSPI Interface Implementation Checklist
      4. 7.2.4 General-Purpose Memory Controller (GPMC)
        1. 7.2.4.1 IO Power Supply
        2. 7.2.4.2 GPMC Interface
        3. 7.2.4.3 Memory (Attached Device) Reset
        4. 7.2.4.4 Signals Connection
          1. 7.2.4.4.1 GPMC NAND
        5. 7.2.4.5 Capacitors for the Power Supply Rails
        6. 7.2.4.6 GPMC Interface Checklist
    3. 7.3 External Communication Interface (Ethernet (CPSW3G and PRU_ICSSG), USB2.0, USB3.0 (SERDES), PCIe (SERDES), UART and CAN)
      1. 7.3.1 Ethernet Interface (CPSW3G and PRU_ICSSG)
        1. 7.3.1.1  IO Power Supply
        2. 7.3.1.2  Media Independent Interface (MAC side)
          1. 7.3.1.2.1 Common Platform Ethernet Switch 3-Port Gigabit (CPSW3G)
          2. 7.3.1.2.2 Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
          3. 7.3.1.2.3 Additional Information
        3. 7.3.1.3  Usage of SysConfig-PinMux Tool
        4. 7.3.1.4  Ethernet PHY Reset
        5. 7.3.1.5  Ethernet PHY Pin Strapping
        6. 7.3.1.6  Ethernet PHY (and MAC) Operation and Media Independent Interface (MII) Clock
          1. 7.3.1.6.1 Crystal
          2. 7.3.1.6.2 Oscillator
          3. 7.3.1.6.3 Processor Clock Output (CLKOUT0)
        7. 7.3.1.7  MAC (Data, Control and Clock) Interface Signals Connection
        8. 7.3.1.8  External Interrupt (EXTINTn)
          1. 7.3.1.8.1 External Interrupt (EXTINTn) Checklist
        9. 7.3.1.9  MAC (Media Access Controller) to MAC Interface
        10. 7.3.1.10 MDIO (Management Data Input/Output) Interface
          1. 7.3.1.10.1 MDIO Interface Mode
        11. 7.3.1.11 Ethernet MDI (Medium Dependent Interface) Including Magnetics
        12. 7.3.1.12 Capacitors for the Power Supply Rails
        13. 7.3.1.13 Ethernet Interface Checklist
      2. 7.3.2 Universal Serial Bus (USB2.0)
        1. 7.3.2.1 USB Used
          1. 7.3.2.1.1 USB Host Interface
          2. 7.3.2.1.2 USB Device Interface
          3. 7.3.2.1.3 USB Dual-Role Device Interface
          4. 7.3.2.1.4 USB Type-C®
        2. 7.3.2.2 USB Not Used
        3. 7.3.2.3 Additional Information
        4. 7.3.2.4 USB Interface Checklist
      3. 7.3.3 Serializer and Deserializer (SERDES)
        1. 7.3.3.1 SERDES0 Checklist
        2. 7.3.3.2 SERDES0 Used
          1. 7.3.3.2.1 USB3SS0 - USB3.0 Super Speed Interface Configuration
            1. 7.3.3.2.1.1 Signal Interface
              1. 7.3.3.2.1.1.1 USB3.0 Super Speed Interface
                1. 7.3.3.2.1.1.1.1 USB3.0 Super Speed Interface Operating Mode Configuration
            2. 7.3.3.2.1.2 Unused SERDES Clock Connection
            3. 7.3.3.2.1.3 Additional Information
            4. 7.3.3.2.1.4 USB3SS0 - USB3.0 Super Speed Interface Checklist
          2. 7.3.3.2.2 Peripheral Component Interconnect Express (PCIe) Interface Configuration
            1. 7.3.3.2.2.1 Clock Configuration for PCIe Operating Modes
            2. 7.3.3.2.2.2 Signal Interface Termination
            3. 7.3.3.2.2.3 PCIe Clock (REFCLK) Source
            4. 7.3.3.2.2.4 Hardware Reset (Cold or Fundamental Reset)
            5. 7.3.3.2.2.5 PCIe Clock Request (PCIE0_CLKREQn) Signal
            6. 7.3.3.2.2.6 Connecting PCIe Interface Signals
            7. 7.3.3.2.2.7 PCIe Interface Checklist
        3. 7.3.3.3 SERDES0 Not Used
      4. 7.3.4 Universal Asynchronous Receiver/Transmitter (UART)
        1. 7.3.4.1 Universal Asynchronous Receiver/Transmitter (UART) Checklist
      5. 7.3.5 Controller Area Network (CAN)
        1. 7.3.5.1 Controller Area Network Checklist
    4. 7.4 On-Board Synchronous Communication Interfaces (MCSPI, FSI and I2C)
      1. 7.4.1 Multichannel Serial Peripheral Interface (MCSPI)
        1. 7.4.1.1 MCSPI Checklist
      2. 7.4.2 FSI (Fast Serial Interface)
        1. 7.4.2.1 FSI0 Checklist
      3. 7.4.3 Inter-Integrated Circuit (I2C)
        1. 7.4.3.1 I2C (Open-drain Output Type Buffer) Interface Checklist
        2. 7.4.3.2 I2C (Emulated Open-drain Output Type Buffer) Interface Checklist
    5. 7.5 Analog to Digital Converter (ADC)
      1. 7.5.1 ADC0 Used
      2. 7.5.2 ADC0 Not Used
      3. 7.5.3 ADC0 Configured as ADC0_DIG_TEST[0-7]
      4. 7.5.4 ADC0 Checklist
    6. 7.6 GPIO and Hardware Diagnostics
      1. 7.6.1 General Purpose Input/Output (GPIO)
        1. 7.6.1.1 Connection and External Buffering
        2. 7.6.1.2 GPIO Multiplexed With MMC Interface
        3. 7.6.1.3 Additional Information
        4. 7.6.1.4 GPIO Checklist
      2. 7.6.2 On-Board Hardware Diagnostics
        1. 7.6.2.1 Monitoring of On-board Supply Voltages Using Processor Voltage Monitors
          1. 7.6.2.1.1 Voltage Monitor Pins Used
            1. 7.6.2.1.1.1 Voltage Monitor Checklist
          2. 7.6.2.1.2 Voltage Monitor Pins Not Used
        2. 7.6.2.2 Internal Temperature Monitoring
          1. 7.6.2.2.1 Internal Temperature Monitoring Checklist
        3. 7.6.2.3 Connection of Error Signal Output (MCU_SAFETY_ERRORn)
        4. 7.6.2.4 High Frequency Oscillator (MCU_OSC0) Clock Loss Detection
    7. 7.7 Verifying Board Level Design Issues
      1. 7.7.1 Processor Pin Configuration Using Pinmux Tool
      2. 7.7.2 Schematics Configurations
      3. 7.7.3 Connecting Supply Rails to Pullups
      4. 7.7.4 Peripheral (Subsystem) Clock Outputs
      5. 7.7.5 General Board Bring-up and Debug
        1. 7.7.5.1 Clock Output for Board Bring-Up, Test or Debug
        2. 7.7.5.2 Additional Information
        3. 7.7.5.3 General Board Bring-up and Debug Checklist
  11. 8 Self-Review of the Custom Board Schematics Design
  12. 9 Layout Notes (Added on the Schematic)
    1. 9.1 Layout Checklist
  13. 10Custom Board Design Simulation
  14. 11Additional References
    1. 11.1 AM6xx FAQs
    2. 11.2 FAQs - Processor Product Family Wise and Sitara Processor Families
    3. 11.3 Attached Devices
  15. 12Summary
  16. 13References
    1. 13.1 AM64x
    2. 13.2 AM243x
    3. 13.3 Common References
    4. 13.4 Master List of Available FAQs - Processor Family Wise
    5. 13.5 Master List of Available FAQs - Sitara Processor Families
    6. 13.6 Software FAQs
    7. 13.7 FAQs for Attached Devices
  17.   A Terminology
  18.   Revision History
Application Note

AM6442 , AM6422 , AM6412 and AM2434 Processor Schematic Design Guidelines and Schematic Review Checklist