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LM27403 Synchronous Buck Controller With Temperature-Compensated, Inductor-DCR-Based Overcurrent Protection and Programmable Thermal Shutdown
SNVS896B
August 2013 – November 2014
LM27403
PRODUCTION DATA.
CONTENTS
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LM27403 Synchronous Buck Controller With Temperature-Compensated, Inductor-DCR-Based Overcurrent Protection and Programmable Thermal Shutdown
1
Features
2
Applications
3
Description
4
Revision History
5
Description (Continued)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
Handling Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Input Range: VIN
8.3.2
Output Voltage: FB Voltage and Accuracy
8.3.3
Input and Bias Rail Voltages: VIN and VDD
8.3.4
Precision Enable: UVLO/EN
8.3.5
Switching Frequency
8.3.5.1
Frequency Adjust: FADJ
8.3.5.2
Clock Synchronization: SYNC
8.3.6
Temperature Sensing: D+ and D-
8.3.7
Thermal Shutdown: OTP
8.3.8
Inductor-DCR-Based Overcurrent Protection
8.3.9
Current Sensing: CS+ and CS-
8.3.10
Current Limit Handling
8.3.11
Soft-Start: SS/TRACK
8.3.11.1
Tracking
8.3.12
Monotonic Startup
8.3.13
Prebias Startup
8.3.14
Voltage-Mode Control
8.3.15
Output Voltage Remote Sense: RS
8.3.16
Power Good: PGOOD
8.3.17
Gate Drivers: LG and HG
8.3.18
Sink and Source Capability
8.4
Device Functional Modes
8.4.1
Fault Conditions
8.4.1.1
Thermal Shutdown
8.4.1.2
Current Limit and Short Circuit Operation (Positive Overcurrent)
8.4.1.3
Negative Current Limit
8.4.1.4
Undervoltage Threshold (UVT)
8.4.1.5
Overvoltage Threshold (OVT)
9
Application and Implementation
9.1
Application Information
9.1.1
Design and Implementation
9.1.2
Power Train Components
9.1.2.1
Filter Inductor
9.1.2.2
Output Capacitors
9.1.2.3
Input Capacitors
9.1.2.4
Power MOSFETs
9.1.3
Control Loop Compensation
9.2
Typical Applications
9.2.1
Design 1 - High-Efficiency Synchronous Buck Regulator for Telecom Power
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
Design 2 - Powering FPGAs Using Flexible 30A Regulator With Small Footprint
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.3
Application Curves
9.2.3
Design 3 - Powering Multicore DSPs
9.2.4
Design 4 - Regulated 12-V Rail with LDO Low-Noise Auxiliary Output for RF Power
9.2.5
Design 5 - High Power Density Implementation From 3.3-V or 5-V Supply Rail
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
Power Stage Layout
11.1.2
Gate Drive Layout
11.1.3
Controller Layout
11.1.4
Thermal Design and Layout
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Development Support
12.1.2
Third-Party Products Disclaimer
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
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