SNAS675A October   2015  – November 2015 LMK61PD0A2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Control
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - Power Supply
    6. 7.6  LVPECL Output Characteristics
    7. 7.7  LVDS Output Characteristics
    8. 7.8  HCSL Output Characteristics
    9. 7.9  OE Input Characteristics
    10. 7.10 OS, FS[1:0] Input Characteristics
    11. 7.11 Frequency Tolerance Characteristics
    12. 7.12 Power-On/Reset Characteristics (VDD)
    13. 7.13 PSRR Characteristics
    14. 7.14 PLL Clock Output Jitter Characteristics
    15. 7.15 Additional Reliability and Qualification
    16. 7.16 Typical Performance Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Device Output Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Block-Level Description
      2. 9.3.2 Device Configuration Control
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Jitter Considerations in Serdes Systems
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ensuring Thermal Reliability
      2. 12.1.2 Best Practices for Signal Integrity
      3. 12.1.3 Recommended Solder Reflow Profile
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

1 Features

  • Ultra-low Noise, High Performance
    • Jitter: 90 fs RMS typical fOUT > 100 MHz
    • PSRR: -70 dBc, robust supply noise immunity
  • Flexible Output Frequency and Format; User Selectable
    • Frequencies: 62.5 MHz, 100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 312.5 MHz
    • Formats: LVPECL, LVDS or HCSL
  • Total frequency tolerance of ± 50 ppm
  • Internal memory stores multiple start-up configurations, selectable through pin control
  • 3.3V operating voltage
  • Industrial temperature range (-40ºC to +85ºC)
  • 7 mm x 5 mm 8-pin package

2 Applications

  • High-performance replacement for crystal-, SAW-, or silicon-based Oscillators
  • Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN
  • Test and Measurement
  • Medical Imaging
  • FPGA, Processor Attach

3 Description

The LMK61PD0A2 is an ultra-low jitter PLLatinumTM pin selectable oscillator that generates commonly used reference clocks. The device is pre-programmed in factory to support seven unique reference clock frequencies that can be selected by pin-strapping each of FS[1:0] to VDD, GND or NC (no connect). Output format is selected between LVPECL, LVDS, or HCSL by pin-strapping OS to VDD, GND or NC. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMK61PD0A2 8-pin QFM (SIA) 7.0 mm x 5.0 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Pinout and Simplified Block Diagram

LMK61PD0A2 pinout_functional_block_diagram_snas675.gif