SNAA411 September   2024 CDCLVC1102 , CDCLVC1103 , CDCLVC1104 , CDCLVC1110 , CDCLVD1204 , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK01801 , LMK04832 , LMK1C1102 , LMK1C1103 , LMK1C1104 , LMK1C1106 , LMK1C1108 , LMK1D1204 , LMK1D1208 , LMX2485 , LMX2491 , LMX2572 , LMX2592 , LMX2594 , LMX2595 , LMX2820

1.   1
2.   Abstract
3.   Trademarks
4. 1Generic Clock Tree
5. 2Sine Wave Slew Rate Requirement
6. 3Current Approach vs Clock Buffer
7. 4Clock Buffer Implementation
   1. 4.1 Clock Buffer Common Input Stages
   2. 4.2 Choosing Between Internal or External DC Bias
   3. 4.3 Single Ended or LVCMOS Signal
   4. 4.4 Differential Inputs
8. 5Performance Improvements, Results With Clock Buffer
   1. 5.1 FSWP Phase Noise Analyzer Measurements Case
   2. 5.2 TI LMX2820 Noise Improvements With Sine to Square Wave Clock Buffer
      1. 5.2.1 LMX2820 Phase Noise and RMS Jitter Results Summary
9. 6Sine to Square Wave Clock Buffer Comparison
   1. 6.1 LMK1C110x Additive Noise vs Others
10. 7Summary
11. 8References

Sine to Square Wave Conversion Using Clock Buffers