SLVSDF5D September   2017  – October 2019 TPS50601A-SP

PRODUCTION DATA.  

  1. 1 Features
    1.     Efficiency at VIN = PVIN = 5 V
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Safe Start-Up Into Prebiased Outputs
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Slope Compensation
      7. 7.3.7  Enable and Adjust UVLO
      8. 7.3.8  Adjustable Switching Frequency and Synchronization (SYNC)
      9. 7.3.9  Slow Start (SS/TR)
      10. 7.3.10 Power Good (PWRGD)
      11. 7.3.11 Sequencing (SS/TR)
      12. 7.3.12 Output Overvoltage Protection (OVP)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.13.2 Low-Side MOSFET Overcurrent Protection
      14. 7.3.14 Thermal Shutdown
      15. 7.3.15 Turn-On Behavior
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed-Frequency PWM Control
      2. 7.4.2 Continuous Current Mode (CCM) Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Operating Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Slow Start Capacitor Selection
        5. 8.2.2.5 Undervoltage Lockout (UVLO) Set Point
        6. 8.2.2.6 Output Voltage Feedback Resistor Selection
        7. 8.2.2.7 Compensation Component Selection
      3. 8.2.3 Parallel Operation
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

1 Features

  • 5962-10221:
    • Radiation hardened up to TID 100 krad(Si)
    • ELDRS free 100 krad(Si) – 10 mrad(Si)/s
    • Single lhup (SEL) Immune to
      LET = 75 MeV-cm2/mg
    • SEB and SEGR immune to 75 MeV-cm2/mg, SOA Curve Available
    • SET/SEFI Cross-section plot available
  • peak efficiency: 96.6% (VO = 3.3 V)
  • Integrated 58-mΩ/50-mΩ MOSFETs
  • Power rail: 3 to 7 V on VIN
  • 6-A Maximum output current
  • Flexible switching frequency options:
    • 100-kHz to 1-MHz Adjustable internal oscillator
    • External sync capability: 100 kHz to 1 MHz
    • Sync pin can be configured as a 500-kHz output for master/slave applications
  • 0.804-V ±1.5% Voltage reference overtemperature, radiation, and line and load regulation
  • Monotonic start-up into prebiased outputs
  • Adjustable soft start through external capacitor
  • Input enable and power-good output for power sequencing
  • Power good output monitor for undervoltage and overvoltage
  • Adjustable input undervoltage lockout (UVLO)
  • 20-Pin Ultra-small, thermally-enhanced ceramic flatpack package (hkh) for space applications

    • Efficiency at VIN = PVIN = 5 V

    TPS50601A-SP D001_SLVSDF5.gif