SLLSEL2C September   2015  – July 2016 SN65DP149 , SN75DP149

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 HPD Switching Characteristics
    12. 7.12 DDC and I2C Switching Characteristics
    13. 7.13 Parameter Measurement Information
    14. 7.14 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reset Implementation
      2. 8.3.2 Operation Timing
      3. 8.3.3 Input Lane Swap and Polarity Working
      4. 8.3.4 Main Link Inputs
      5. 8.3.5 Main Link Inputs Debug Tools
      6. 8.3.6 Receiver Equalizer
      7. 8.3.7 Termination Impedance Control
      8. 8.3.8 TMDS Outputs
        1. 8.3.8.1 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Functional Description
    5. 8.5 Register Maps
      1. 8.5.1 DP-HDMI Adaptor ID Buffer
      2. 8.5.2 Local I2C Interface Overview
      3. 8.5.3 I2C Control Behavior
      4. 8.5.4 I2C Control and Status Registers
        1. 8.5.4.1 Bit Access Tag Conventions
        2. 8.5.4.2 CSR Bit Field Definitions
          1. 8.5.4.2.1 ID Registers
          2. 8.5.4.2.2 Misc Control
          3. 8.5.4.2.3 HDMI Control
          4. 8.5.4.2.4 Equalization Control Register
          5. 8.5.4.2.5 EyeScan Control Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Use Case of SNx5DP149
      2. 9.1.2 DDC Pullup Resistors
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Example
      1. 9.3.1 Compliance Testing
  10. 10Power Supply Recommendations
    1. 10.1 Power Management
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

1 Features

  • DisplayPort™ Physical Layer Input Port to TMDS Physical Layer Output Port Supporting up to
    3.4-Gbps Data Rates
  • Support DisplayPort Dual-Mode Standard Version 1.1
  • Support HDMI1.4b Transmitter Electrical Parameters
  • Integrated TMDS Level Translator and CDR
  • Adaptive Receiver Equalizer and Programmable Fixed Equalizer
  • Selectable De-Emphasis
  • Low Power Typical Consumption
    • 390 mW at 3.4-Gbps Retimer
    • 10 mW at Shutdown State
  • Integrated DVI and HDMI Identification Recognition Dual Mode DP Type 2 Capability
  • Active I2C[4] Buffer
  • Input Swap on Main Lanes
  • I2C[4] and Pin-Strap Programmable
  • Industrial Temperature Range:
    –40 to 85°C (SN65DP149)
  • Extended Commercial Temperature Range:
    0 to 85°C (SN75DP149)
  • 40-Pin 0.4-mm Pitch, 5-mm × 5-mm WQFN

2 Applications

  • Personal Computer Market
  • Next Generation Adaptor Dongles
  • Desktop PC
  • Notebook PC Market
  • Docking Station
  • HDTV
  • Standalone Video Card
  • Tablet

3 Description

The SNx5DP149 device is a dual mode[1] DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b output signals. The SNx5DP149 device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link. The SNx5DP149 device supports data rate up to 3.4-Gbps per data lane to support Ultra HD (4K × 2K / 30-Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 × 1080 / 60-Hz). The SNx5DP149 device can automatically configure itself as a re-driver at data rates <1 Gbps, or as a retimer at more than this data rate. This feature can be turned off through I2C[4] programming.

For signal integrity, the SNx5DP149 device implements several features. The SNx5DP149 receiver supports both adaptive and fixed equalization to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces or cables. When working as a retimer, the embedded clock data recovery (CDR) cleans up the input high frequency and random jitter from video source. The transmitter provides several features for passing compliance and reducing system-level design issues like de-emphasis, which compensates for the attenuation when driving long cables or high-loss board traces. The SNx5DP149 device also includes TMDS output amplitude adjust using an external resistor on the Vsadj pin, source termination selection, and output slew rate control. Device operation and configuration can be programmed by pin strapping or I2C[4].

The SNx5DP149 device implements several methods for power management and active power reduction.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN65DP149
SN75DP149		 WQFN (40) 5.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

DP149 Mother Board Application Structure

SN65DP149 SN75DP149 diag_motherboard_SLLSEJ2.gif

DP149 Dongle Application Structure

SN65DP149 SN75DP149 diag_dongle_SLLSEJ2.gif