The ADS7066 device features a bidirectional CRC module. When CRC is enabled, the ADS7066 sends data with a CRC byte appened to the host to be evaluated by the host. For incoming data to the ADS7066, the host will send the data with a CRC byte appended to be evaluated by the ADS7066.

For each data frame, a CRC code is calculated based on the generator polynomial and the data payload in the frame. The ADS7066 implements the CRC-8-CCITT polynomial, shown in ADS7066 Register Read Timing Diagram With CRC Enabled, and is pre-set with 1 data values(1111 1111b). The host and ADC append a CRC code on transmitted data. Each device also computes that the CRC code received is correct based on the data received. This allows for instant detection of communication errors over the SPI bus.

Equation 1.

When the CRC module is enabled in the ADS7066 device, the communication bus will need to use 32-bit SPI frames, usually comprised of a 24-bit data payload and an 8-bit CRC byte; zeros should be used to fill the 32-bit data frame if needed. The timing diagram in Figure 1-1 illustrates a completed data transfer of the ADS7066 CRC of a typical register read with CRC enabled.

Due to the elongated communication frames, the throughput rate is decreased. Each frame will be eight clock pulses longer than expected with CRC enable. For example, without CRC enabled, the clock rate needed to achieve a sampling rate of 500 kSPS would be 8 Mhz. This is based on only outputing conversion data without any status flags included, which means one frame is completed with 16 SCLK pulses. When CRC is enabled, the SPI frame now needs to be 32 SCLK pulses. If the clock frequency is maintained at 8 Mhz, then the sampling rate has now decreased from 500kSPS to 250 kSPS. This is due to the longer SPI frames needed. To achieve the target sampling rate of 500 kSPS with CRC enabled the clock rate will need to be increased from 8 Mhz to 16 Mhz to compensate for the longer SPI frame.

After the data integrity check of recomputing the CRC calculation and there are no errors detected, then all commands continue as expected.

If a CRC error occurs, meaning an error in the expected CRC value does not match the CRC value transmitted, then the ADS7066 device will not execute the command where the error was detected. Thereafter, the device will no longer respond to any register writes, but will respond to read commands and provide ADC conversion measurements. During this time, correct CRC codes are still needed for read commands sent to the device. When the error is detected, the device will set a status flag that notifies the user a CRC error has occured. The device will return back to normal operation once the status flag is cleared. Until the CRC status error flag is cleared the device will not respond to any write commands other than a write command to clear the CRC error status flag.

ADS7066 Register Read Timing Diagram With CRC Enabled

For more details on this, see the CRCERR_IN register in the ADS7066 Small, 8-Channel, 16-Bit SAR ADC With GPIOs Data Sheet. To help calculate the CRC code for the ADS7066 device, TI provides a ADS7066 CRC Calculator available in the ADS7066 Product Folder. For further reading about CRC and other data inegrity methods, see the Communication Methods for Data Integrity Using DeltaSigma Data Converters Application Report.